include/configs/adp-ag102.h

   1 /*
   2  * Copyright (C) 2011 Andes Technology Corporation
   3  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include <asm/arch/ag102.h>
  12
  13 /*
  14  * CPU and Board Configuration Options
  15  */
  16 #define CONFIG_ADP_AG102
  17
  18 #define CONFIG_USE_INTERRUPT
  19
  20 #define CONFIG_SKIP_LOWLEVEL_INIT
  21
  22 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  23 #define CONFIG_MEM_REMAP
  24 #endif
  25
  26 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  27 #define CONFIG_SYS_TEXT_BASE    0x04200000
  28 #else
  29 #define CONFIG_SYS_TEXT_BASE    0x00000000
  30 #endif
  31
  32 /*
  33  * Timer
  34  */
  35
  36 /*
  37  * According to the discussion in u-boot mailing list before,
  38  * CONFIG_SYS_HZ at 1000 is mandatory.
  39  */
  40 #define CONFIG_SYS_HZ           1000
  41 #define CONFIG_SYS_CLK_FREQ     (66000000 * 2)
  42 #define VERSION_CLOCK           CONFIG_SYS_CLK_FREQ
  43
  44 /*
  45  * Use Externel CLOCK or PCLK
  46  */
  47 #undef CONFIG_FTRTC010_EXTCLK
  48
  49 #ifndef CONFIG_FTRTC010_EXTCLK
  50 #define CONFIG_FTRTC010_PCLK
  51 #endif
  52
  53 #ifdef CONFIG_FTRTC010_EXTCLK
  54 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  55 #else
  56 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  57 #endif
  58
  59 #define TIMER_LOAD_VAL  0xffffffff
  60
  61 /*
  62  * Real Time Clock
  63  */
  64 #define CONFIG_RTC_FTRTC010
  65
  66 /*
  67  * Real Time Clock Divider
  68  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  69  */
  70 #define OSC_5MHZ                        (5*1000000)
  71 #define OSC_CLK                         (2*OSC_5MHZ)
  72 #define RTC_DIV_COUNT                   (OSC_CLK/OSC_5MHZ)
  73
  74 /*
  75  * Serial console configuration
  76  */
  77
  78 /* FTUART is a high speed NS 16C550A compatible UART */
  79 #define CONFIG_BAUDRATE                 38400
  80 #define CONFIG_CONS_INDEX               1
  81 #define CONFIG_SYS_NS16550
  82 #define CONFIG_SYS_NS16550_SERIAL
  83 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_01_BASE
  84 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  85 #define CONFIG_SYS_NS16550_CLK          33000000        /* AG102 */
  86
  87 /*
  88  * Ethernet
  89  */
  90 #define CONFIG_NET_MULTI
  91 #define CONFIG_PHY_MAX_ADDR     32      /* this comes from <linux/phy.h> */
  92 #define CONFIG_SYS_DISCOVER_PHY
  93 #define CONFIG_FTGMAC100
  94 #define CONFIG_FTGMAC100_EGIGA
  95
  96 #define CONFIG_BOOTDELAY        3
  97
  98 /*
  99  * SD (MMC) controller
 100  */
 101 #define CONFIG_MMC
 102 #define CONFIG_CMD_MMC
 103 #define CONFIG_GENERIC_MMC
 104 #define CONFIG_DOS_PARTITION
 105 #define CONFIG_FTSDC010
 106 #define CONFIG_FTSDC010_NUMBER          1
 107 #define CONFIG_FTSDC010_SDIO
 108 #define CONFIG_CMD_FAT
 109 #define CONFIG_CMD_EXT2
 110
 111 /*
 112  * Command line configuration.
 113  */
 114 #include <config_cmd_default.h>
 115
 116 #define CONFIG_CMD_CACHE
 117 #define CONFIG_CMD_DATE
 118 #define CONFIG_CMD_PING
 119 #define CONFIG_CMD_IDE
 120 #define CONFIG_CMD_FAT
 121 #define CONFIG_CMD_ELF
 122
 123 #undef CONFIG_CMD_FLASH
 124 #undef CONFIG_CMD_IMLS
 125
 126 /*
 127  * PCI
 128  */
 129 #define CONFIG_PCI
 130 #define CONFIG_FTPCI100
 131 #define CONFIG_PCI_INDIRECT_BRIDGE
 132 #define CONFIG_FTPCI100_MEM_BASE        0xa0000000
 133 #define CONFIG_FTPCI100_IO_SIZE         FTPCI100_BASE_IO_SIZE(256) /* 256M */
 134 #define CONFIG_FTPCI100_MEM_SIZE        FTPCI100_MEM_SIZE(128)  /* 128M */
 135 #define CONFIG_FTPCI100_MEM_BASE_SIZE1  0x50
 136
 137 #define CONFIG_PCI_MEM_BUS      0xa0000000
 138 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
 139 #define CONFIG_PCI_MEM_SIZE     0x01000000              /* 256M */
 140
 141 #define CONFIG_PCI_IO_BUS       0x90000000
 142 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
 143 #define CONFIG_PCI_IO_SIZE      0x00100000              /* 1M */
 144
 145 /*
 146  * USB
 147  */
 148 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
 149 #if defined(CONFIG_FTPCI100)
 150 #define __io /* enable outl & inl */
 151 #define CONFIG_CMD_USB
 152 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS      5
 153 #define CONFIG_USB_STORAGE
 154 #define CONFIG_USB_EHCI
 155 #define CONFIG_PCI_EHCI_DEVICE 0
 156 #define CONFIG_USB_EHCI_PCI
 157 #define CONFIG_PREBOOT                          "usb start;"
 158 #endif /* #if defiend(CONFIG_FTPCI100) */
 159 #endif /* #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) */
 160
 161 /*
 162  * IDE/ATA stuff
 163  */
 164 #define __io
 165 #define CONFIG_IDE_AHB
 166 #define CONFIG_IDE_FTIDE020
 167
 168 #undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
 169 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 170 #define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 171 #define CONFIG_IDE_PREINIT      1       /* preinit for ide              */
 172
 173 /* max: 2 IDE busses */
 174 #define CONFIG_SYS_IDE_MAXBUS           1       /* origin: 2 */
 175 /* max: 2 drives per IDE bus */
 176 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* origin: (MAXBUS * 2) */
 177
 178 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_FTIDE020S_BASE
 179 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 180 #define CONFIG_SYS_ATA_IDE1_OFFSET      0x0000
 181
 182 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* for data I/O */
 183 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* for normal regs access */
 184 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0000  /* for alternate regs */
 185
 186 #define CONFIG_MAC_PARTITION
 187 #define CONFIG_DOS_PARTITION
 188 #define CONFIG_SUPPORT_VFAT
 189
 190 /*
 191  * Miscellaneous configurable options
 192  */
 193 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 194 #define CONFIG_SYS_PROMPT       "NDS32 # "      /* Monitor Command Prompt */
 195 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 196
 197 /* Print Buffer Size */
 198 #define CONFIG_SYS_PBSIZE       \
 199         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 200
 201 /* max number of command args */
 202 #define CONFIG_SYS_MAXARGS      16
 203
 204 /* Boot Argument Buffer Size */
 205 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 206
 207 /*
 208  * Size of malloc() pool
 209  */
 210 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128 * 1024)
 211
 212 /*
 213  * size in bytes reserved for initial data
 214 */
 215 #define CONFIG_SYS_GBL_DATA_SIZE        128
 216
 217 /*
 218  * AHB Controller configuration
 219  */
 220 #define CONFIG_FTAHBC020S
 221
 222 #ifdef CONFIG_FTAHBC020S
 223 #include <faraday/ftahbc020s.h>
 224
 225 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
 226 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE    0x100
 227
 228 /*
 229  * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
 230  * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
 231  * in C language.
 232  */
 233 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
 234         (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
 235                                          FTAHBC020S_SLAVE_BSR_SIZE(0xb))
 236 #endif
 237
 238 /*
 239  * Watchdog
 240  */
 241 #define CONFIG_FTWDT010_WATCHDOG
 242
 243 /*
 244  * PCU Power Control Unit configuration
 245  */
 246 #define CONFIG_ANDES_PCU
 247
 248 #ifdef CONFIG_ANDES_PCU
 249 #include <andestech/andes_pcu.h>
 250
 251 #endif
 252
 253 /*
 254  * DDR DRAM controller configuration
 255  */
 256 #define CONFIG_DWCDDR21MCTL
 257
 258 #ifdef CONFIG_DWCDDR21MCTL
 259 #include <synopsys/dwcddr21mctl.h>
 260 /* DCR:
 261  *   2GB: 0x000025d2, 2GB (1Gb x8 2 ranks) Micron/innoDisk/Transcend
 262  *   1GB: 0x000021d2, 1GB (1Gb x8 1 rank) Micron/Transcend/innoDisk
 263  * 512MB: 0x000025cc, Micron 512MB (512Mb x16 2 ranks)
 264  * 512MB: 0x000021ca, Trenscend/innoDisk 512MB (512Mb x8 1 rank)
 265  * 256MB: 0x000020d4, Micron 256MB (1Gb x16 1 ranks)
 266  */
 267 #define CONFIG_SYS_DWCDDR21MCTL_CCR     0x00020004
 268 #define CONFIG_SYS_DWCDDR21MCTL_CCR2    (DWCDDR21MCTL_CCR_DTT(0x1)      | \
 269                                         DWCDDR21MCTL_CCR_DFTLM(0x4)     | \
 270                                         DWCDDR21MCTL_CCR_HOSTEN(0x1))
 271
 272 /* 0x04: 0x000020d4 */
 273 #define CONFIG_SYS_DWCDDR21MCTL_DCR     0x000020ca
 274
 275 /* 0x08: 0x0000000f */
 276 #define CONFIG_SYS_DWCDDR21MCTL_IOCR    0x0000000f
 277
 278 /* 0x10: 0x00034812 */
 279 #define CONFIG_SYS_DWCDDR21MCTL_DRR     (DWCDDR21MCTL_DRR_TRFC(0x12)    | \
 280                                         DWCDDR21MCTL_DRR_TRFPRD(0x0348))
 281 /* 0x24 */
 282 #define CONFIG_SYS_DWCDDR21MCTL_DLLCR0  DWCDDR21MCTL_DLLCR_PHASE(0x0)
 283
 284 /* 0x4c: 0x00000040 */
 285 #define CONFIG_SYS_DWCDDR21MCTL_RSLR0   0x00000040
 286
 287 /* 0x5c: 0x000055CF */
 288 #define CONFIG_SYS_DWCDDR21MCTL_RDGR0   0x000055cf
 289
 290 /* 0xa4: 0x00100000 */
 291 #define CONFIG_SYS_DWCDDR21MCTL_DTAR    (DWCDDR21MCTL_DTAR_DTBANK(0x0)  | \
 292                                         DWCDDR21MCTL_DTAR_DTROW(0x0100) | \
 293                                         DWCDDR21MCTL_DTAR_DTCOL(0x0))
 294 /* 0x1f0: 0x00000852 */
 295 #define CONFIG_SYS_DWCDDR21MCTL_MR      (DWCDDR21MCTL_MR_WR(0x4)        | \
 296                                         DWCDDR21MCTL_MR_CL(0x5)         | \
 297                                         DWCDDR21MCTL_MR_BL(0x2))
 298 #endif
 299
 300 /*
 301  * Physical Memory Map
 302  */
 303 #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
 304 #define PHYS_SDRAM_0            0x00000000      /* SDRAM Bank #1 */
 305 #if defined(CONFIG_MEM_REMAP)
 306 #define PHYS_SDRAM_0_AT_INIT    0x80000000      /* SDRAM Bank #1 before remap*/
 307 #endif
 308 #else   /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
 309 #define PHYS_SDRAM_0            0x80000000      /* SDRAM Bank #1 */
 310 #endif
 311
 312 #define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of DRAM */
 313 #define PHYS_SDRAM_0_SIZE       0x10000000      /* 256 MB */
 314
 315 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
 316
 317 #ifdef CONFIG_MEM_REMAP
 318 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
 319                                         GENERATED_GBL_DATA_SIZE)
 320 #else
 321 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 322                                         GENERATED_GBL_DATA_SIZE)
 323 #endif /* CONFIG_MEM_REMAP */
 324
 325 /*
 326  * Load address and memory test area should agree with
 327  * board/faraday/a320/config.mk
 328  * Be careful not to overwrite U-boot itself.
 329  */
 330 #define CONFIG_SYS_LOAD_ADDR            0x0CF00000
 331
 332 /* memtest works on 63 MB in DRAM */
 333 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_0
 334 #define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_0 + 0x03F00000)
 335
 336 /*
 337  * Static memory controller configuration
 338  */
 339
 340 /*
 341  * FLASH and environment organization
 342  */
 343 #define CONFIG_SYS_NO_FLASH
 344
 345 /*
 346  * Env Storage Settings
 347  */
 348 #define CONFIG_ENV_IS_NOWHERE
 349 #define CONFIG_ENV_SIZE                 4096
 350
 351 #endif  /* __CONFIG_H */