include/configs/adp-ag102.h

   1 /*
   2  * Copyright (C) 2011 Andes Technology Corporation
   3  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #ifndef __CONFIG_H
  24 #define __CONFIG_H
  25
  26 #include <asm/arch/ag102.h>
  27
  28 /*
  29  * CPU and Board Configuration Options
  30  */
  31 #define CONFIG_ADP_AG102
  32
  33 #define CONFIG_USE_INTERRUPT
  34
  35 #define CONFIG_SKIP_LOWLEVEL_INIT
  36
  37 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  38 #define CONFIG_MEM_REMAP
  39 #endif
  40
  41 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  42 #define CONFIG_SYS_TEXT_BASE    0x04200000
  43 #else
  44 #define CONFIG_SYS_TEXT_BASE    0x00000000
  45 #endif
  46
  47 /*
  48  * Timer
  49  */
  50
  51 /*
  52  * According to the discussion in u-boot mailing list before,
  53  * CONFIG_SYS_HZ at 1000 is mandatory.
  54  */
  55 #define CONFIG_SYS_HZ           1000
  56 #define CONFIG_SYS_CLK_FREQ     (66000000 * 2)
  57 #define VERSION_CLOCK           CONFIG_SYS_CLK_FREQ
  58
  59 /*
  60  * Use Externel CLOCK or PCLK
  61  */
  62 #undef CONFIG_FTRTC010_EXTCLK
  63
  64 #ifndef CONFIG_FTRTC010_EXTCLK
  65 #define CONFIG_FTRTC010_PCLK
  66 #endif
  67
  68 #ifdef CONFIG_FTRTC010_EXTCLK
  69 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  70 #else
  71 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  72 #endif
  73
  74 #define TIMER_LOAD_VAL  0xffffffff
  75
  76 /*
  77  * Real Time Clock
  78  */
  79 #define CONFIG_RTC_FTRTC010
  80
  81 /*
  82  * Real Time Clock Divider
  83  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  84  */
  85 #define OSC_5MHZ                        (5*1000000)
  86 #define OSC_CLK                         (2*OSC_5MHZ)
  87 #define RTC_DIV_COUNT                   (OSC_CLK/OSC_5MHZ)
  88
  89 /*
  90  * Serial console configuration
  91  */
  92
  93 /* FTUART is a high speed NS 16C550A compatible UART */
  94 #define CONFIG_BAUDRATE                 38400
  95 #define CONFIG_CONS_INDEX               1
  96 #define CONFIG_SYS_NS16550
  97 #define CONFIG_SYS_NS16550_SERIAL
  98 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_01_BASE
  99 #define CONFIG_SYS_NS16550_REG_SIZE     -4
 100 #define CONFIG_SYS_NS16550_CLK          33000000        /* AG102 */
 101
 102 /*
 103  * Ethernet
 104  */
 105 #define CONFIG_NET_MULTI
 106 #define CONFIG_PHY_MAX_ADDR     32      /* this comes from <linux/phy.h> */
 107 #define CONFIG_SYS_DISCOVER_PHY
 108 #define CONFIG_FTGMAC100
 109 #define CONFIG_FTGMAC100_EGIGA
 110
 111 #define CONFIG_BOOTDELAY        3
 112
 113 /*
 114  * SD (MMC) controller
 115  */
 116 #define CONFIG_MMC
 117 #define CONFIG_CMD_MMC
 118 #define CONFIG_GENERIC_MMC
 119 #define CONFIG_DOS_PARTITION
 120 #define CONFIG_FTSDC010
 121 #define CONFIG_FTSDC010_NUMBER          1
 122 #define CONFIG_FTSDC010_SDIO
 123 #define CONFIG_CMD_FAT
 124 #define CONFIG_CMD_EXT2
 125
 126 /*
 127  * Command line configuration.
 128  */
 129 #include <config_cmd_default.h>
 130
 131 #define CONFIG_CMD_CACHE
 132 #define CONFIG_CMD_DATE
 133 #define CONFIG_CMD_PING
 134 #define CONFIG_CMD_IDE
 135 #define CONFIG_CMD_FAT
 136 #define CONFIG_CMD_ELF
 137
 138 #undef CONFIG_CMD_FLASH
 139 #undef CONFIG_CMD_IMLS
 140
 141 /*
 142  * PCI
 143  */
 144 #define CONFIG_PCI
 145 #define CONFIG_FTPCI100
 146 #define CONFIG_PCI_INDIRECT_BRIDGE
 147 #define CONFIG_FTPCI100_MEM_BASE        0xa0000000
 148 #define CONFIG_FTPCI100_IO_SIZE         FTPCI100_BASE_IO_SIZE(256) /* 256M */
 149 #define CONFIG_FTPCI100_MEM_SIZE        FTPCI100_MEM_SIZE(128)  /* 128M */
 150 #define CONFIG_FTPCI100_MEM_BASE_SIZE1  0x50
 151
 152 #define CONFIG_PCI_MEM_BUS      0xa0000000
 153 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
 154 #define CONFIG_PCI_MEM_SIZE     0x01000000              /* 256M */
 155
 156 #define CONFIG_PCI_IO_BUS       0x90000000
 157 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
 158 #define CONFIG_PCI_IO_SIZE      0x00100000              /* 1M */
 159
 160 /*
 161  * USB
 162  */
 163 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
 164 #if defined(CONFIG_FTPCI100)
 165 #define __io /* enable outl & inl */
 166 #define CONFIG_CMD_USB
 167 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS      5
 168 #define CONFIG_USB_STORAGE
 169 #define CONFIG_USB_EHCI
 170 #define CONFIG_PCI_EHCI_DEVICE 0
 171 #define CONFIG_USB_EHCI_PCI
 172 #define CONFIG_PREBOOT                          "usb start;"
 173 #endif /* #if defiend(CONFIG_FTPCI100) */
 174 #endif /* #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) */
 175
 176 /*
 177  * IDE/ATA stuff
 178  */
 179 #define __io
 180 #define CONFIG_IDE_AHB
 181 #define CONFIG_IDE_FTIDE020
 182
 183 #undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
 184 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 185 #define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 186 #define CONFIG_IDE_PREINIT      1       /* preinit for ide              */
 187
 188 /* max: 2 IDE busses */
 189 #define CONFIG_SYS_IDE_MAXBUS           1       /* origin: 2 */
 190 /* max: 2 drives per IDE bus */
 191 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* origin: (MAXBUS * 2) */
 192
 193 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_FTIDE020S_BASE
 194 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 195 #define CONFIG_SYS_ATA_IDE1_OFFSET      0x0000
 196
 197 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* for data I/O */
 198 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* for normal regs access */
 199 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0000  /* for alternate regs */
 200
 201 #define CONFIG_MAC_PARTITION
 202 #define CONFIG_DOS_PARTITION
 203 #define CONFIG_SUPPORT_VFAT
 204
 205 /*
 206  * Miscellaneous configurable options
 207  */
 208 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 209 #define CONFIG_SYS_PROMPT       "NDS32 # "      /* Monitor Command Prompt */
 210 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 211
 212 /* Print Buffer Size */
 213 #define CONFIG_SYS_PBSIZE       \
 214         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 215
 216 /* max number of command args */
 217 #define CONFIG_SYS_MAXARGS      16
 218
 219 /* Boot Argument Buffer Size */
 220 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 221
 222 /*
 223  * Size of malloc() pool
 224  */
 225 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128 * 1024)
 226
 227 /*
 228  * size in bytes reserved for initial data
 229 */
 230 #define CONFIG_SYS_GBL_DATA_SIZE        128
 231
 232 /*
 233  * AHB Controller configuration
 234  */
 235 #define CONFIG_FTAHBC020S
 236
 237 #ifdef CONFIG_FTAHBC020S
 238 #include <faraday/ftahbc020s.h>
 239
 240 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
 241 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE    0x100
 242
 243 /*
 244  * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
 245  * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
 246  * in C language.
 247  */
 248 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
 249         (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
 250                                          FTAHBC020S_SLAVE_BSR_SIZE(0xb))
 251 #endif
 252
 253 /*
 254  * Watchdog
 255  */
 256 #define CONFIG_FTWDT010_WATCHDOG
 257
 258 /*
 259  * PCU Power Control Unit configuration
 260  */
 261 #define CONFIG_ANDES_PCU
 262
 263 #ifdef CONFIG_ANDES_PCU
 264 #include <andestech/andes_pcu.h>
 265
 266 #endif
 267
 268 /*
 269  * DDR DRAM controller configuration
 270  */
 271 #define CONFIG_DWCDDR21MCTL
 272
 273 #ifdef CONFIG_DWCDDR21MCTL
 274 #include <synopsys/dwcddr21mctl.h>
 275 /* DCR:
 276  *   2GB: 0x000025d2, 2GB (1Gb x8 2 ranks) Micron/innoDisk/Transcend
 277  *   1GB: 0x000021d2, 1GB (1Gb x8 1 rank) Micron/Transcend/innoDisk
 278  * 512MB: 0x000025cc, Micron 512MB (512Mb x16 2 ranks)
 279  * 512MB: 0x000021ca, Trenscend/innoDisk 512MB (512Mb x8 1 rank)
 280  * 256MB: 0x000020d4, Micron 256MB (1Gb x16 1 ranks)
 281  */
 282 #define CONFIG_SYS_DWCDDR21MCTL_CCR     0x00020004
 283 #define CONFIG_SYS_DWCDDR21MCTL_CCR2    (DWCDDR21MCTL_CCR_DTT(0x1)      | \
 284                                         DWCDDR21MCTL_CCR_DFTLM(0x4)     | \
 285                                         DWCDDR21MCTL_CCR_HOSTEN(0x1))
 286
 287 /* 0x04: 0x000020d4 */
 288 #define CONFIG_SYS_DWCDDR21MCTL_DCR     0x000020ca
 289
 290 /* 0x08: 0x0000000f */
 291 #define CONFIG_SYS_DWCDDR21MCTL_IOCR    0x0000000f
 292
 293 /* 0x10: 0x00034812 */
 294 #define CONFIG_SYS_DWCDDR21MCTL_DRR     (DWCDDR21MCTL_DRR_TRFC(0x12)    | \
 295                                         DWCDDR21MCTL_DRR_TRFPRD(0x0348))
 296 /* 0x24 */
 297 #define CONFIG_SYS_DWCDDR21MCTL_DLLCR0  DWCDDR21MCTL_DLLCR_PHASE(0x0)
 298
 299 /* 0x4c: 0x00000040 */
 300 #define CONFIG_SYS_DWCDDR21MCTL_RSLR0   0x00000040
 301
 302 /* 0x5c: 0x000055CF */
 303 #define CONFIG_SYS_DWCDDR21MCTL_RDGR0   0x000055cf
 304
 305 /* 0xa4: 0x00100000 */
 306 #define CONFIG_SYS_DWCDDR21MCTL_DTAR    (DWCDDR21MCTL_DTAR_DTBANK(0x0)  | \
 307                                         DWCDDR21MCTL_DTAR_DTROW(0x0100) | \
 308                                         DWCDDR21MCTL_DTAR_DTCOL(0x0))
 309 /* 0x1f0: 0x00000852 */
 310 #define CONFIG_SYS_DWCDDR21MCTL_MR      (DWCDDR21MCTL_MR_WR(0x4)        | \
 311                                         DWCDDR21MCTL_MR_CL(0x5)         | \
 312                                         DWCDDR21MCTL_MR_BL(0x2))
 313 #endif
 314
 315 /*
 316  * Physical Memory Map
 317  */
 318 #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
 319 #define PHYS_SDRAM_0            0x00000000      /* SDRAM Bank #1 */
 320 #if defined(CONFIG_MEM_REMAP)
 321 #define PHYS_SDRAM_0_AT_INIT    0x80000000      /* SDRAM Bank #1 before remap*/
 322 #endif
 323 #else   /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
 324 #define PHYS_SDRAM_0            0x80000000      /* SDRAM Bank #1 */
 325 #endif
 326
 327 #define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of DRAM */
 328 #define PHYS_SDRAM_0_SIZE       0x10000000      /* 256 MB */
 329
 330 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
 331
 332 #ifdef CONFIG_MEM_REMAP
 333 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
 334                                         GENERATED_GBL_DATA_SIZE)
 335 #else
 336 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 337                                         GENERATED_GBL_DATA_SIZE)
 338 #endif /* CONFIG_MEM_REMAP */
 339
 340 /*
 341  * Load address and memory test area should agree with
 342  * board/faraday/a320/config.mk
 343  * Be careful not to overwrite U-boot itself.
 344  */
 345 #define CONFIG_SYS_LOAD_ADDR            0x0CF00000
 346
 347 /* memtest works on 63 MB in DRAM */
 348 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_0
 349 #define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_0 + 0x03F00000)
 350
 351 /*
 352  * Static memory controller configuration
 353  */
 354
 355 /*
 356  * FLASH and environment organization
 357  */
 358 #define CONFIG_SYS_NO_FLASH
 359
 360 /*
 361  * Env Storage Settings
 362  */
 363 #define CONFIG_ENV_IS_NOWHERE
 364 #define CONFIG_ENV_SIZE                 4096
 365
 366 #endif  /* __CONFIG_H */