include/configs/aev.h

   1 /*
   2  * (C) Copyright 2003-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004-2005
   6  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * High Level Configuration Options
  32  * (easy to change)
  33  */
  34
  35 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  36 #define CONFIG_MPC5200          1       /* (more precisely an MPC5200 CPU) */
  37 #define CONFIG_TQM5200          1       /* ... on TQM5200 module */
  38 #undef CONFIG_TQM5200_REV100            /*  define for revision 100 modules */
  39 #define CONFIG_STK52XX          1       /* ... on a STK52XX base board */
  40 #define CONFIG_STK52XX_REV100   1       /*  define for revision 100 baseboards */
  41 #define CONFIG_AEVFIFO          1
  42 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33.000000MHz */
  43
  44 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  45 #define BOOTFLAG_WARM           0x02    /* Software reboot           */
  46
  47 /*
  48  * Serial console configuration
  49  */
  50 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  51 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  52 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  53
  54 /*
  55  * PCI Mapping:
  56  * 0x40000000 - 0x4fffffff - PCI Memory
  57  * 0x50000000 - 0x50ffffff - PCI IO Space
  58  */
  59 #ifdef CONFIG_AEVFIFO
  60 #define CONFIG_PCI              1
  61 #define CONFIG_PCI_PNP          1
  62 /* #define CONFIG_PCI_SCAN_SHOW 1 */
  63
  64 #define CONFIG_PCI_MEM_BUS      0x40000000
  65 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  66 #define CONFIG_PCI_MEM_SIZE     0x10000000
  67
  68 #define CONFIG_PCI_IO_BUS       0x50000000
  69 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  70 #define CONFIG_PCI_IO_SIZE      0x01000000
  71
  72 #define CONFIG_NET_MULTI        1
  73 #define CONFIG_EEPRO100         1
  74 #define CFG_RX_ETH_BUFFER       8  /* use 8 rx buffer on eepro100  */
  75 #define CONFIG_NS8382X          1
  76 #endif  /* CONFIG_AEVFIFO */
  77
  78 /* Partitions */
  79 #define CONFIG_MAC_PARTITION
  80 #define CONFIG_DOS_PARTITION
  81 #define CONFIG_ISO_PARTITION
  82
  83 /* POST support */
  84 #define CONFIG_POST             (CFG_POST_MEMORY   | \
  85                                  CFG_POST_CPU      | \
  86                                  CFG_POST_I2C)
  87
  88 #ifdef CONFIG_POST
  89 /* preserve space for the post_word at end of on-chip SRAM */
  90 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
  91 #endif
  92
  93
  94 /*
  95  * BOOTP options
  96  */
  97 #define CONFIG_BOOTP_BOOTFILESIZE
  98 #define CONFIG_BOOTP_BOOTPATH
  99 #define CONFIG_BOOTP_GATEWAY
 100 #define CONFIG_BOOTP_HOSTNAME
 101
 102
 103 /*
 104  * Command line configuration.
 105  */
 106 #include <config_cmd_default.h>
 107
 108 #define CONFIG_CMD_ASKENV
 109 #define CONFIG_CMD_DATE
 110 #define CONFIG_CMD_DHCP
 111 #define CONFIG_CMD_ECHO
 112 #define CONFIG_CMD_EEPROM
 113 #define CONFIG_CMD_I2C
 114 #define CONFIG_CMD_MII
 115 #define CONFIG_CMD_NFS
 116 #define CONFIG_CMD_PCI
 117 #define CONFIG_CMD_PING
 118 #define CONFIG_CMD_REGINFO
 119 #define CONFIG_CMD_SNTP
 120
 121 #ifdef CONFIG_POST
 122 #define CONFIG_CMD_DIAG
 123 #endif
 124
 125
 126 #define CONFIG_TIMESTAMP                /* display image timestamps */
 127
 128 #if (TEXT_BASE == 0xFC000000)           /* Boot low */
 129 #   define CFG_LOWBOOT          1
 130 #endif
 131
 132 /*
 133  * Autobooting
 134  */
 135 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 136
 137 #define CONFIG_PREBOOT  "echo;" \
 138         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 139         "echo"
 140
 141 #undef  CONFIG_BOOTARGS
 142
 143 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 144         "netdev=eth0\0"                                                 \
 145         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 146         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 147         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 148                 "nfsroot=${serverip}:${rootpath} "                      \
 149                 "console=ttyS0,${baudrate}\0"                           \
 150         "addip=setenv bootargs ${bootargs} "                            \
 151                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 152                 ":${hostname}:${netdev}:off panic=1\0"                  \
 153         "flash_self=run ramargs addip;"                                 \
 154                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 155         "flash_nfs=run nfsargs addip;"                                  \
 156                 "bootm ${kernel_addr}\0"                                \
 157         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 158         "bootfile=/tftpboot/tqm5200/uImage\0"                           \
 159         "load=tftp 200000 ${u-boot}\0"                                  \
 160         "u-boot=/tftpboot/tqm5200/u-boot.bin\0"                         \
 161         "update=protect off FC000000 FC05FFFF;"                         \
 162                 "erase FC000000 FC05FFFF;"                              \
 163                 "cp.b 200000 FC000000 ${filesize};"                     \
 164                 "protect on FC000000 FC05FFFF\0"                        \
 165         ""
 166
 167 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 168
 169 /*
 170  * IPB Bus clocking configuration.
 171  */
 172 #define CFG_IPBCLK_EQUALS_XLBCLK                /* define for 133MHz speed */
 173
 174 #if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 175 /*
 176  * PCI Bus clocking configuration
 177  *
 178  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 179  * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 180  * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 181  */
 182 #define CFG_PCICLK_EQUALS_IPBCLK_DIV2   /* define for 66MHz speed */
 183 #endif
 184
 185 /*
 186  * I2C configuration
 187  */
 188 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 189 #ifdef CONFIG_TQM5200_REV100
 190 #define CFG_I2C_MODULE          1       /* Select I2C module #1 for rev. 100 board */
 191 #else
 192 #define CFG_I2C_MODULE          2       /* Select I2C module #2 for all other revs */
 193 #endif
 194
 195 /*
 196  * I2C clock frequency
 197  *
 198  * Please notice, that the resulting clock frequency could differ from the
 199  * configured value. This is because the I2C clock is derived from system
 200  * clock over a frequency divider with only a few divider values. U-boot
 201  * calculates the best approximation for CFG_I2C_SPEED. However the calculated
 202  * approximation allways lies below the configured value, never above.
 203  */
 204 #define CFG_I2C_SPEED           100000 /* 100 kHz */
 205 #define CFG_I2C_SLAVE           0x7F
 206
 207 /*
 208  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
 209  * also). For other EEPROMs configuration should be verified. On Mini-FAP the
 210  * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
 211  * same configuration could be used.
 212  */
 213 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x */
 214 #define CFG_I2C_EEPROM_ADDR_LEN         2
 215 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* =32 Bytes per write */
 216 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  20
 217
 218 /*
 219  * Flash configuration
 220  */
 221 #define CFG_FLASH_BASE          TEXT_BASE /* 0xFC000000 */
 222
 223 /* use CFI flash driver if no module variant is spezified */
 224 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant */
 225 #define CFG_FLASH_CFI_DRIVER    1       /* Use the common driver */
 226 #define CFG_FLASH_BANKS_LIST    { CFG_BOOTCS_START }
 227 #define CFG_FLASH_EMPTY_INFO
 228 #define CFG_FLASH_SIZE          0x04000000 /* 64 MByte */
 229 #define CFG_MAX_FLASH_SECT      512     /* max num of sects on one chip */
 230 #undef CFG_FLASH_USE_BUFFER_WRITE       /* not supported yet for AMD */
 231
 232 #if !defined(CFG_LOWBOOT)
 233 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
 234 #else   /* CFG_LOWBOOT */
 235 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00060000)
 236 #endif  /* CFG_LOWBOOT */
 237 #define CFG_MAX_FLASH_BANKS     1       /* max num of flash banks
 238                                            (= chip selects) */
 239 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 240 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 241
 242
 243 /*
 244  * Environment settings
 245  */
 246 #define CFG_ENV_IS_IN_FLASH     1
 247 #define CFG_ENV_SIZE            0x10000
 248 #define CFG_ENV_SECT_SIZE       0x20000
 249 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 250 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 251
 252 /*
 253  * Memory map
 254  */
 255 #define CFG_MBAR                0xF0000000
 256 #define CFG_SDRAM_BASE          0x00000000
 257 #define CFG_DEFAULT_MBAR        0x80000000
 258
 259 /* Use ON-Chip SRAM until RAM will be available */
 260 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 261 #ifdef CONFIG_POST
 262 /* preserve space for the post_word at end of on-chip SRAM */
 263 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_POST_SIZE
 264 #else
 265 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE
 266 #endif
 267
 268
 269 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 270 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 271 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 272
 273 #define CFG_MONITOR_BASE        TEXT_BASE
 274 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 275 #   define CFG_RAMBOOT          1
 276 #endif
 277
 278 #define CFG_MONITOR_LEN         (384 << 10)     /* Reserve 384 kB for Monitor   */
 279 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 280 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 281
 282 /*
 283  * Ethernet configuration
 284  */
 285 #define CONFIG_MPC5xxx_FEC      1
 286 /*
 287  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 288  */
 289 /* #define CONFIG_FEC_10MBIT 1 */
 290 #define CONFIG_PHY_ADDR         0x00
 291
 292 /*
 293  * GPIO configuration
 294  *
 295  * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
 296  *      Bit 0 (mask: 0x80000000): 1
 297  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 298  *      00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
 299  *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
 300  *            Use for REV200 STK52XX boards. Do not use with REV100 modules
 301  *            (because, there I2C1 is used as I2C bus)
 302  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 303  * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
 304  *      000 -> All PSC2 pins are GIOPs
 305  *      001 -> CAN1/2 on PSC2 pins
 306  *             Use for REV100 STK52xx boards
 307  * use PSC6:
 308  *   on STK52xx:
 309  *      use as UART. Pins PSC6_0 to PSC6_3 are used.
 310  *      Bits 9:11 (mask: 0x00700000):
 311  *         101 -> PSC6 : Extended POST test is not available
 312  *   on MINI-FAP and TQM5200_IB:
 313  *      use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
 314  *         000 -> PSC6 could not be used as UART, CODEC or IrDA
 315  *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
 316  *   tests.
 317  */
 318 #define CFG_GPS_PORT_CONFIG     0x81500014
 319
 320 /*
 321  * RTC configuration
 322  */
 323 #define CONFIG_RTC_MPC5200      1       /* use internal MPC5200 RTC */
 324
 325 /*
 326  * Miscellaneous configurable options
 327  */
 328 #define CFG_LONGHELP                    /* undef to save memory     */
 329 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 330 #if defined(CONFIG_CMD_KGDB)
 331 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 332 #else
 333 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 334 #endif
 335 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 336 #define CFG_MAXARGS             16      /* max number of command args   */
 337 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 338
 339 /* Enable an alternate, more extensive memory test */
 340 #define CFG_ALT_MEMTEST
 341
 342 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 343 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 344
 345 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 346
 347 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 348
 349 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs */
 350 #if defined(CONFIG_CMD_KGDB)
 351 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 352 #endif
 353
 354 /*
 355  * Enable loopw command.
 356  */
 357 #define CONFIG_LOOPW
 358
 359 /*
 360  * Various low-level settings
 361  */
 362 #if defined(CONFIG_MPC5200)
 363 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 364 #define CFG_HID0_FINAL          HID0_ICE
 365 #else
 366 #define CFG_HID0_INIT           0
 367 #define CFG_HID0_FINAL          0
 368 #endif
 369
 370 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 371 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 372 #ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 373 #define CFG_BOOTCS_CFG          0x0008DF30 /* for pci_clk  = 66 MHz */
 374 #else
 375 #define CFG_BOOTCS_CFG          0x0004DF30 /* for pci_clk = 33 MHz */
 376 #endif
 377 #define CFG_CS0_START           CFG_FLASH_BASE
 378 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 379
 380 #define CONFIG_LAST_STAGE_INIT
 381
 382 /*
 383  * SRAM - Do not map below 2 GB in address space, because this area is used
 384  * for SDRAM autosizing.
 385  */
 386 #define CFG_CS2_START           0xE5000000
 387 #define CFG_CS2_SIZE            0x80000         /* 512 kByte */
 388 #define CFG_CS2_CFG             0x0004D930
 389
 390 /*
 391  * Grafic controller - Do not map below 2 GB in address space, because this
 392  * area is used for SDRAM autosizing.
 393  */
 394 #define SM501_FB_BASE           0xE0000000
 395 #define CFG_CS1_START           (SM501_FB_BASE)
 396 #define CFG_CS1_SIZE            0x4000000       /* 64 MByte */
 397 #define CFG_CS1_CFG             0x8F48FF70
 398 #define SM501_MMIO_BASE         CFG_CS1_START + 0x03E00000
 399
 400 #define CFG_CS_BURST            0x00000000
 401 #define CFG_CS_DEADCYCLE        0x33333311      /* 1 dead cycle for flash and SM501 */
 402
 403 #define CFG_RESET_ADDRESS       0xff000000
 404
 405 #endif /* __CONFIG_H */