include/configs/alpr.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*-----------------------------------------------------------------------
  12  * High Level Configuration Options
  13  *----------------------------------------------------------------------*/
  14 #define CONFIG_ALPR             1           /* Board is ebony           */
  15 #define CONFIG_440GX            1           /* Specifc GX support       */
  16 #define CONFIG_440              1           /* ... PPC440 family        */
  17 #define CONFIG_4xx              1           /* ... PPC4xx family        */
  18 #define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_pre_init      */
  19 #define CONFIG_LAST_STAGE_INIT  1           /* call last_stage_init()   */
  20
  21 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  22
  23 #define CONFIG_SYS_CLK_FREQ     33333333    /* external freq to pll     */
  24 #define CONFIG_4xx_DCACHE               /* Enable i- and d-cache        */
  25
  26 /*-----------------------------------------------------------------------
  27  * Base addresses -- Note these are effective addresses where the
  28  * actual resources get mapped (not physical addresses)
  29  *----------------------------------------------------------------------*/
  30 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* _must_ be 0                  */
  31 #define CONFIG_SYS_FLASH_BASE           0xffe00000      /* start of FLASH               */
  32 #define CONFIG_SYS_MONITOR_BASE 0xfffc0000      /* start of monitor             */
  33 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory            */
  34 #define CONFIG_SYS_PCI_MEMSIZE          0x40000000      /* size of mapped pci memory    */
  35 #define CONFIG_SYS_ISRAM_BASE           0xc0000000      /* internal SRAM                */
  36 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs            */
  37 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  38 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  39 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  40
  41
  42 #define CONFIG_SYS_FPGA_BASE        (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
  43 #define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
  44
  45 /*-----------------------------------------------------------------------
  46  * Initial RAM & stack pointer (placed in internal SRAM)
  47  *----------------------------------------------------------------------*/
  48 #define CONFIG_SYS_TEMP_STACK_OCM  1
  49 #define CONFIG_SYS_OCM_DATA_ADDR   CONFIG_SYS_ISRAM_BASE
  50 #define CONFIG_SYS_INIT_RAM_ADDR   CONFIG_SYS_ISRAM_BASE  /* Initial RAM address        */
  51 #define CONFIG_SYS_INIT_RAM_SIZE    0x2000          /* Size of used area in RAM */
  52
  53 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  54 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  55
  56 #define CONFIG_SYS_MONITOR_LEN      (256 * 1024)    /* Reserve 256 kB for Mon   */
  57 #define CONFIG_SYS_MALLOC_LEN       (128 * 1024)    /* Reserve 128 kB for malloc*/
  58
  59 /*-----------------------------------------------------------------------
  60  * Serial Port
  61  *----------------------------------------------------------------------*/
  62 #define CONFIG_CONS_INDEX       2       /* Use UART1                    */
  63 #define CONFIG_SYS_NS16550
  64 #define CONFIG_SYS_NS16550_SERIAL
  65 #define CONFIG_SYS_NS16550_REG_SIZE     1
  66 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  67
  68 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK
  69 #define CONFIG_BAUDRATE         115200
  70
  71 #define CONFIG_SYS_BAUDRATE_TABLE  \
  72     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  73
  74 /*-----------------------------------------------------------------------
  75  * FLASH related
  76  *----------------------------------------------------------------------*/
  77 #define CONFIG_SYS_FLASH_CFI            1       /* The flash is CFI compatible          */
  78 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use common CFI driver                */
  79 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
  80 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
  81 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
  82 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
  83 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash        */
  84
  85 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
  86
  87 #define CONFIG_ENV_SECT_SIZE    0x10000 /* size of one complete sector          */
  88 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
  89 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
  90
  91 /* Address and size of Redundant Environment Sector     */
  92 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
  93 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
  94
  95 /*-----------------------------------------------------------------------
  96  * DDR SDRAM
  97  *----------------------------------------------------------------------*/
  98 #undef CONFIG_SPD_EEPROM                /* Don't use SPD EEPROM for setup       */
  99 #define CONFIG_SDRAM_BANK0      1       /* init onboard DDR SDRAM bank 0        */
 100 #undef CONFIG_SDRAM_ECC                 /* enable ECC support                   */
 101 #define CONFIG_SYS_SDRAM_TABLE  { \
 102                 {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
 103                 {(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)  */
 104
 105 /*-----------------------------------------------------------------------
 106  * I2C
 107  *----------------------------------------------------------------------*/
 108 #define CONFIG_SYS_I2C
 109 #define CONFIG_SYS_I2C_PPC4XX
 110 #define CONFIG_SYS_I2C_PPC4XX_CH0
 111 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
 112 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 113 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }   /* Don't probe these addrs */
 114
 115 /*-----------------------------------------------------------------------
 116  * I2C EEPROM (PCF8594C)
 117  *----------------------------------------------------------------------*/
 118 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x54    /* EEPROM PCF8594C              */
 119 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 120 /* mask of address bits that overflow into the "EEPROM chip address"    */
 121 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 122 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3     /* The Philips PCF8594C has     */
 123                                         /* 8 byte page write mode using */
 124                                         /* last 3 bits of the address   */
 125 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   40   /* and takes up to 40 msec */
 126
 127 #define CONFIG_PREBOOT  "echo;" \
 128         "echo Type \"run kernelx\" to boot the system;"                 \
 129         "echo"
 130
 131 #undef  CONFIG_BOOTARGS
 132
 133 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 134         "netdev=eth3\0"                                                 \
 135         "hostname=alpr\0"                                               \
 136         "fdt_file=alpr/alpr.dtb\0"                                      \
 137         "fdt_addr=400000\0"                                             \
 138         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 139                 "nfsroot=${serverip}:${rootpath} ${init}\0"             \
 140         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 141         "addip=setenv bootargs ${bootargs} "                            \
 142                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 143                 ":${hostname}:${netdev}:off panic=1\0"                  \
 144         "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
 145                 "mem=193M\0"                                            \
 146         "flash_nfs=run nfsargs addip addtty;"                           \
 147                 "bootm ${kernel_addr}\0"                                \
 148         "flash_self=run ramargs addip addtty;"                          \
 149                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 150         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 151                 "bootm\0"                                               \
 152         "net_nfs_fdt=tftp 200000 ${bootfile};"                          \
 153                 "tftp ${fdt_addr} ${fdt_file};"                         \
 154                 "run nfsargs addip addtty;"                             \
 155                 "bootm 200000 - ${fdt_addr}\0"                          \
 156         "rootpath=/opt/projects/alpr/nfs_root\0"                        \
 157         "bootfile=/alpr/uImage\0"                                       \
 158         "kernel_addr=fff00000\0"                                        \
 159         "ramdisk_addr=fff10000\0"                                       \
 160         "load=tftp 100000 /alpr/u-boot/u-boot.bin\0"                    \
 161         "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"   \
 162                 "cp.b 100000 fffc0000 40000;"                           \
 163                 "setenv filesize;saveenv\0"                             \
 164         "upd=run load update\0"                                         \
 165         "ethprime=ppc_4xx_eth3\0"                                       \
 166         "ethact=ppc_4xx_eth3\0"                                         \
 167         "autoload=no\0"                                                 \
 168         "ipconfig=dhcp;setenv serverip 11.0.0.152\0"                    \
 169         "load_fpga=fpga load 0 ffe00000 10dd9a\0"                       \
 170         "mtdargs=setenv bootargs root=/dev/mtdblock6 rw "               \
 171                 "rootfstype=jffs2 init=/sbin/init\0"                    \
 172         "kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
 173                 ";bootm 200000\0"                                       \
 174         "kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \
 175                 "addtty;bootm 200000\0"                                 \
 176         "kernel1=setenv actkernel 'kernel1';run load_fpga "             \
 177                 "kernel1_mtd\0"                                         \
 178         "kernel2=setenv actkernel 'kernel2';run load_fpga "             \
 179                 "kernel2_mtd\0"                                         \
 180         ""
 181
 182 #define CONFIG_BOOTCOMMAND      "run kernel2"
 183
 184 #define CONFIG_BOOTDELAY        2       /* autoboot after 5 seconds     */
 185
 186 #define CONFIG_BAUDRATE         115200
 187
 188 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 189 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 190
 191 #define CONFIG_PPC4xx_EMAC
 192 #define CONFIG_MII              1       /* MII PHY management           */
 193 #define CONFIG_PHY_ADDR         0x02    /* dummy setting, no EMAC0 used */
 194 #define CONFIG_PHY1_ADDR        0x03    /* dummy setting, no EMAC1 used */
 195 #define CONFIG_PHY2_ADDR        0x01    /* PHY address for EMAC2        */
 196 #define CONFIG_PHY3_ADDR        0x02    /* PHY address for EMAC3        */
 197 #define CONFIG_HAS_ETH0
 198 #define CONFIG_HAS_ETH1
 199 #define CONFIG_HAS_ETH2
 200 #define CONFIG_HAS_ETH3
 201 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 202 #define CONFIG_M88E1111_PHY     1       /* needed for PHY specific setup*/
 203 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 204 #define CONFIG_SYS_RX_ETH_BUFFER        32      /* Number of ethernet rx buffers & descriptors */
 205
 206 #define CONFIG_NETCONSOLE               /* include NetConsole support   */
 207
 208
 209 /*
 210  * BOOTP options
 211  */
 212 #define CONFIG_BOOTP_BOOTFILESIZE
 213 #define CONFIG_BOOTP_BOOTPATH
 214 #define CONFIG_BOOTP_GATEWAY
 215 #define CONFIG_BOOTP_HOSTNAME
 216
 217
 218 /*
 219  * Command line configuration.
 220  */
 221 #include <config_cmd_default.h>
 222
 223 #define CONFIG_CMD_DHCP
 224 #define CONFIG_CMD_EEPROM
 225 #define CONFIG_CMD_FPGA
 226 #define CONFIG_CMD_I2C
 227 #undef CONFIG_CMD_LOADB
 228 #undef CONFIG_CMD_LOADS
 229 #define CONFIG_CMD_MII
 230 #define CONFIG_CMD_NAND
 231 #define CONFIG_CMD_NET
 232 #undef CONFIG_CMD_NFS
 233 #define CONFIG_CMD_PCI
 234
 235 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 236
 237 /*
 238  * Miscellaneous configurable options
 239  */
 240 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 241 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 242 #if defined(CONFIG_CMD_KGDB)
 243 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 244 #else
 245 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 246 #endif
 247 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 248 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 249 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 250
 251 #define CONFIG_SYS_ALT_MEMTEST          1       /* Enable more extensive memtest*/
 252 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 253 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 254
 255 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 256 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 257
 258 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 259
 260 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 261 #define CONFIG_LOOPW            1       /* enable loopw command         */
 262 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 263 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 264 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 265
 266 #define CONFIG_SYS_4xx_RESET_TYPE       0x2     /* use chip reset on this board */
 267
 268 /*-----------------------------------------------------------------------
 269  * PCI stuff
 270  *-----------------------------------------------------------------------
 271  */
 272 /* General PCI */
 273 #define CONFIG_PCI                      /* include pci support          */
 274 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 275 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 276 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 277 #define CONFIG_SYS_PCI_TARGBASE    0x80000000   /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 278 #define CONFIG_PCI_BOOTDELAY    1       /* enable pci bootdelay variable*/
 279
 280 /* Board-specific PCI */
 281 #define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
 282 #define CONFIG_SYS_PCI_MASTER_INIT
 283
 284 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC */
 285 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever */
 286
 287 /*-----------------------------------------------------------------------
 288  * FPGA stuff
 289  *-----------------------------------------------------------------------*/
 290 #define CONFIG_FPGA
 291 #define CONFIG_FPGA_ALTERA
 292 #define CONFIG_FPGA_CYCLON2
 293 #define CONFIG_SYS_FPGA_CHECK_CTRLC
 294 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 295 #define CONFIG_FPGA_COUNT       1               /* Ich habe 2 ... aber in
 296                                         Reihe geschaltet -> sollte gehen,
 297                                         aufpassen mit Datasize ist jetzt
 298                                         halt doppelt so gross ... Seite 306
 299                                         ist das mit den multiple Device in PS
 300                                         Mode erklaert ...*/
 301
 302 /* FPGA program pin configuration */
 303 #define CONFIG_SYS_GPIO_CLK             18      /* FPGA clk pin (cpu output)            */
 304 #define CONFIG_SYS_GPIO_DATA            19      /* FPGA data pin (cpu output)           */
 305 #define CONFIG_SYS_GPIO_STATUS          20      /* FPGA status pin (cpu input)          */
 306 #define CONFIG_SYS_GPIO_CONFIG          21      /* FPGA CONFIG pin (cpu output)         */
 307 #define CONFIG_SYS_GPIO_CON_DON 22      /* FPGA CONFIG_DONE pin (cpu input)     */
 308
 309 #define CONFIG_SYS_GPIO_SEL_DPR 14      /* cpu output */
 310 #define CONFIG_SYS_GPIO_SEL_AVR 15      /* cpu output */
 311 #define CONFIG_SYS_GPIO_PROG_EN 23      /* cpu output */
 312
 313 /*-----------------------------------------------------------------------
 314  * Definitions for GPIO setup
 315  *-----------------------------------------------------------------------*/
 316 #define CONFIG_SYS_GPIO_SHUTDOWN        (0x80000000 >> 6)
 317 #define CONFIG_SYS_GPIO_SSD_EMPTY       (0x80000000 >> 9)
 318 #define CONFIG_SYS_GPIO_EREADY          (0x80000000 >> 26)
 319 #define CONFIG_SYS_GPIO_REV0            (0x80000000 >> 14)
 320 #define CONFIG_SYS_GPIO_REV1            (0x80000000 >> 15)
 321
 322 /*-----------------------------------------------------------------------
 323  * NAND-FLASH stuff
 324  *-----------------------------------------------------------------------*/
 325 #define CONFIG_SYS_MAX_NAND_DEVICE      4
 326 #define CONFIG_SYS_NAND_BASE            0xF0000000      /* NAND FLASH Base Address      */
 327 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2,   \
 328                                   CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 }
 329 #define CONFIG_SYS_NAND_QUIET_TEST      1       /* don't warn upon unknown NAND flash   */
 330
 331 /*-----------------------------------------------------------------------
 332  * External Bus Controller (EBC) Setup
 333  *----------------------------------------------------------------------*/
 334 #define CONFIG_SYS_FLASH                CONFIG_SYS_FLASH_BASE
 335
 336 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 337 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 338 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
 339
 340 /* Memory Bank 1 (NAND-FLASH) initialization                                    */
 341 #define CONFIG_SYS_EBC_PB1AP            0x01840380      /* TWT=3                        */
 342 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
 343
 344 /*
 345  * For booting Linux, the board info and command line data
 346  * have to be in the first 8 MB of memory, since this is
 347  * the maximum mapped by the Linux kernel during initialization.
 348  */
 349 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 350
 351 #if defined(CONFIG_CMD_KGDB)
 352 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 353 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 354 #endif
 355
 356 /* pass open firmware flat tree */
 357 #define CONFIG_OF_LIBFDT        1
 358 #define CONFIG_OF_BOARD_SETUP   1
 359
 360 #endif  /* __CONFIG_H */