include/configs/alt.h

   1 /*
   2  * include/configs/alt.h
   3  *     This file is alt board configuration.
   4  *
   5  * Copyright (C) 2014 Renesas Electronics Corporation
   6  *
   7  * SPDX-License-Identifier: GPL-2.0
   8  */
   9
  10 #ifndef __ALT_H
  11 #define __ALT_H
  12
  13 #undef DEBUG
  14 #define CONFIG_R8A7794
  15 #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Alt"
  16
  17 #include "rcar-gen2-common.h"
  18
  19 #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
  20 #define CONFIG_SYS_TEXT_BASE    0x70000000
  21 #else
  22 #define CONFIG_SYS_TEXT_BASE    0xE6304000
  23 #endif
  24
  25 #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
  26 #define CONFIG_SYS_INIT_SP_ADDR         0x7003FFFC
  27 #else
  28 #define CONFIG_SYS_INIT_SP_ADDR         0xE633FFFC
  29 #endif
  30 #define STACK_AREA_SIZE                 0xC000
  31 #define LOW_LEVEL_MERAM_STACK \
  32                 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
  33
  34 /* MEMORY */
  35 #define RCAR_GEN2_SDRAM_BASE            0x40000000
  36 #define RCAR_GEN2_SDRAM_SIZE            (1024u * 1024 * 1024)
  37 #define RCAR_GEN2_UBOOT_SDRAM_SIZE      (512 * 1024 * 1024)
  38
  39 /* SCIF */
  40 #define CONFIG_SCIF_CONSOLE
  41
  42 /* FLASH */
  43 #define CONFIG_SPI
  44 #define CONFIG_SH_QSPI
  45 #define CONFIG_SPI_FLASH_QUAD
  46
  47 /* SH Ether */
  48 #define CONFIG_SH_ETHER
  49 #define CONFIG_SH_ETHER_USE_PORT        0
  50 #define CONFIG_SH_ETHER_PHY_ADDR        0x1
  51 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
  52 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
  53 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
  54 #define CONFIG_SH_ETHER_ALIGNE_SIZE 64
  55 #define CONFIG_PHYLIB
  56 #define CONFIG_PHY_MICREL
  57 #define CONFIG_BITBANGMII
  58 #define CONFIG_BITBANGMII_MULTI
  59
  60 /* Board Clock */
  61 #define RMOBILE_XTAL_CLK        20000000u
  62 #define CONFIG_SYS_CLK_FREQ     RMOBILE_XTAL_CLK
  63 #define CONFIG_SH_TMU_CLK_FREQ  (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
  64 #define CONFIG_PLL1_CLK_FREQ    (CONFIG_SYS_CLK_FREQ * 156 / 2)
  65 #define CONFIG_P_CLK_FREQ       (CONFIG_PLL1_CLK_FREQ / 24)
  66
  67 #define CONFIG_SYS_TMU_CLK_DIV  4
  68
  69 /* i2c */
  70 #define CONFIG_SYS_I2C
  71 #define CONFIG_SYS_I2C_SH
  72 #define CONFIG_SYS_I2C_SLAVE            0x7F
  73 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS       3
  74 #define CONFIG_SYS_I2C_SH_SPEED0        400000
  75 #define CONFIG_SYS_I2C_SH_SPEED1        400000
  76 #define CONFIG_SYS_I2C_SH_SPEED2        400000
  77 #define CONFIG_SH_I2C_DATA_HIGH         4
  78 #define CONFIG_SH_I2C_DATA_LOW          5
  79 #define CONFIG_SH_I2C_CLOCK             10000000
  80
  81 #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
  82
  83 /* USB */
  84 #define CONFIG_USB_EHCI_RMOBILE
  85 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  86
  87 /* MMCIF */
  88 #define CONFIG_SH_MMCIF
  89 #define CONFIG_SH_MMCIF_ADDR            0xee200000
  90 #define CONFIG_SH_MMCIF_CLK             48000000
  91
  92 /* Module stop status bits */
  93 /* INTC-RT */
  94 #define CONFIG_SMSTP0_ENA       0x00400000
  95 /* MSIF */
  96 #define CONFIG_SMSTP2_ENA       0x00002000
  97 /* INTC-SYS, IRQC */
  98 #define CONFIG_SMSTP4_ENA       0x00000180
  99 /* SCIF2 */
 100 #define CONFIG_SMSTP7_ENA       0x00080000
 101
 102 /* SDHI */
 103 #define CONFIG_SH_SDHI_FREQ             97500000
 104
 105 #endif /* __ALT_H */