include/configs/am3517_crane.h

   1 /*
   2  * am3517_crane.h - Default configuration for AM3517 CraneBoard.
   3  *
   4  * Author: Srinath.R <srinath@mistralsolutions.com>
   5  *
   6  * Based on include/configs/am3517evm.h
   7  *
   8  * Copyright (C) 2011 Mistral Solutions pvt Ltd
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19 #define CONFIG_OMAP             1       /* in a TI OMAP core */
  20 #define CONFIG_OMAP3_AM3517CRANE        1       /* working with CRANEBOARD */
  21 #define CONFIG_OMAP_COMMON
  22 /* Common ARM Erratas */
  23 #define CONFIG_ARM_ERRATA_454179
  24 #define CONFIG_ARM_ERRATA_430973
  25 #define CONFIG_ARM_ERRATA_621766
  26
  27 #define CONFIG_EMIF4    /* The chip has EMIF4 controller */
  28
  29 #include <asm/arch/cpu.h>               /* get chip and board defs */
  30 #include <asm/arch/omap.h>
  31
  32 /*
  33  * Display CPU and Board information
  34  */
  35 #define CONFIG_DISPLAY_CPUINFO          1
  36 #define CONFIG_DISPLAY_BOARDINFO        1
  37
  38 /* Clock Defines */
  39 #define V_OSCK                  26000000        /* Clock output from T2 */
  40 #define V_SCLK                  (V_OSCK >> 1)
  41
  42 #define CONFIG_MISC_INIT_R
  43
  44 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
  45 #define CONFIG_SETUP_MEMORY_TAGS        1
  46 #define CONFIG_INITRD_TAG               1
  47 #define CONFIG_REVISION_TAG             1
  48
  49 /*
  50  * Size of malloc() pool
  51  */
  52 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB sector */
  53 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (128 << 10))
  54                                                 /* initial data */
  55 /*
  56  * DDR related
  57  */
  58 #define CONFIG_SYS_CS0_SIZE             (256 * 1024 * 1024)
  59
  60 /*
  61  * Hardware drivers
  62  */
  63
  64 /*
  65  * NS16550 Configuration
  66  */
  67 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  68
  69 #define CONFIG_SYS_NS16550_SERIAL
  70 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  71 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  72
  73 /*
  74  * select serial console configuration
  75  */
  76 #define CONFIG_CONS_INDEX               3
  77 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  78 #define CONFIG_SERIAL3                  3       /* UART3 on CRANEBOARD */
  79
  80 /* allow to overwrite serial and ethaddr */
  81 #define CONFIG_ENV_OVERWRITE
  82 #define CONFIG_BAUDRATE                 115200
  83 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  84                                         115200}
  85 #define CONFIG_GENERIC_MMC              1
  86 #define CONFIG_MMC                      1
  87 #define CONFIG_OMAP_HSMMC               1
  88 #define CONFIG_DOS_PARTITION            1
  89
  90 /*
  91  * USB configuration
  92  * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
  93  * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
  94  */
  95 #define CONFIG_USB_AM35X                1
  96 #define CONFIG_USB_MUSB_HCD                     1
  97
  98 #ifdef CONFIG_USB_AM35X
  99
 100 #ifdef CONFIG_USB_MUSB_HCD
 101
 102 #define CONGIG_CMD_STORAGE
 103
 104 #ifdef CONFIG_USB_KEYBOARD
 105 #define CONFIG_SYS_USB_EVENT_POLL
 106 #define CONFIG_PREBOOT "usb start"
 107 #endif /* CONFIG_USB_KEYBOARD */
 108
 109 #endif /* CONFIG_USB_MUSB_HCD */
 110
 111 #ifdef CONFIG_USB_MUSB_UDC
 112 /* USB device configuration */
 113 #define CONFIG_USB_DEVICE               1
 114 #define CONFIG_USB_TTY                  1
 115 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    1
 116 /* Change these to suit your needs */
 117 #define CONFIG_USBD_VENDORID            0x0451
 118 #define CONFIG_USBD_PRODUCTID           0x5678
 119 #define CONFIG_USBD_MANUFACTURER        "Texas Instruments"
 120 #define CONFIG_USBD_PRODUCT_NAME        "AM3517CRANE"
 121 #endif /* CONFIG_USB_MUSB_UDC */
 122
 123 #endif /* CONFIG_USB_AM35X */
 124
 125 /* commands to include */
 126 #define CONFIG_CMD_JFFS2        /* JFFS2 Support                */
 127
 128 #define CONFIG_CMD_NAND         /* NAND support                 */
 129
 130 #define CONFIG_SYS_NO_FLASH
 131 #define CONFIG_SYS_I2C
 132 #define CONFIG_SYS_OMAP24_I2C_SPEED     100000
 133 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
 134 #define CONFIG_SYS_I2C_OMAP34XX
 135
 136 /*
 137  * Board NAND Info.
 138  */
 139 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 140                                                         /* to access nand */
 141 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 142                                                         /* to access */
 143                                                         /* nand at CS0 */
 144
 145 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of */
 146                                                         /* NAND devices */
 147
 148 #define CONFIG_JFFS2_NAND
 149 /* nand device jffs2 lives on */
 150 #define CONFIG_JFFS2_DEV                "nand0"
 151 /* start of jffs2 partition */
 152 #define CONFIG_JFFS2_PART_OFFSET        0x680000
 153 #define CONFIG_JFFS2_PART_SIZE          0xf980000       /* sz of jffs2 part */
 154
 155 /* Environment information */
 156
 157 #define CONFIG_BOOTFILE         "uImage"
 158
 159 #define CONFIG_EXTRA_ENV_SETTINGS \
 160         "loadaddr=0x82000000\0" \
 161         "console=ttyS2,115200n8\0" \
 162         "mmcdev=0\0" \
 163         "mmcargs=setenv bootargs console=${console} " \
 164                 "root=/dev/mmcblk0p2 rw " \
 165                 "rootfstype=ext3 rootwait\0" \
 166         "nandargs=setenv bootargs console=${console} " \
 167                 "root=/dev/mtdblock4 rw " \
 168                 "rootfstype=jffs2\0" \
 169         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 170         "bootscript=echo Running bootscript from mmc ...; " \
 171                 "source ${loadaddr}\0" \
 172         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 173         "mmcboot=echo Booting from mmc ...; " \
 174                 "run mmcargs; " \
 175                 "bootm ${loadaddr}\0" \
 176         "nandboot=echo Booting from nand ...; " \
 177                 "run nandargs; " \
 178                 "nand read ${loadaddr} 280000 400000; " \
 179                 "bootm ${loadaddr}\0" \
 180
 181 #define CONFIG_BOOTCOMMAND \
 182         "mmc dev ${mmcdev}; if mmc rescan; then " \
 183                 "if run loadbootscript; then " \
 184                         "run bootscript; " \
 185                 "else " \
 186                         "if run loaduimage; then " \
 187                                 "run mmcboot; " \
 188                         "else run nandboot; " \
 189                         "fi; " \
 190                 "fi; " \
 191         "else run nandboot; fi"
 192
 193 #define CONFIG_AUTO_COMPLETE    1
 194 /*
 195  * Miscellaneous configurable options
 196  */
 197 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 198 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 199 /* Print Buffer Size */
 200 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 201                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 202 #define CONFIG_SYS_MAXARGS              32      /* max number of command */
 203                                                 /* args */
 204 /* Boot Argument Buffer Size */
 205 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 206 /* memtest works on */
 207 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)
 208 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 209                                         0x01F00000) /* 31MB */
 210
 211 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0) /* default load */
 212                                                                 /* address */
 213
 214 /*
 215  * AM3517 has 12 GP timers, they can be driven by the system clock
 216  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 217  * This rate is divided by a local divisor.
 218  */
 219 #define CONFIG_SYS_TIMERBASE            OMAP34XX_GPT2
 220 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 221
 222 /*-----------------------------------------------------------------------
 223  * Physical Memory Map
 224  */
 225 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 226 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 227 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 228
 229 /*-----------------------------------------------------------------------
 230  * FLASH and environment organization
 231  */
 232
 233 /* **** PISMO SUPPORT *** */
 234 #define CONFIG_SYS_MAX_FLASH_SECT       520     /* max number of sectors */
 235                                                 /* on one chip */
 236 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of flash banks */
 237 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 238
 239 #define CONFIG_SYS_FLASH_BASE           NAND_BASE
 240
 241 /* Monitor at start of flash */
 242 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 243
 244 #define CONFIG_NAND_OMAP_GPMC
 245 #define CONFIG_ENV_IS_IN_NAND           1
 246 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 247
 248 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)     /* 128 KiB sector */
 249 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 250 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 251
 252 /*-----------------------------------------------------------------------
 253  * CFI FLASH driver setup
 254  */
 255 /* timeout values are in ticks */
 256 #define CONFIG_SYS_FLASH_ERASE_TOUT     (100 * CONFIG_SYS_HZ)
 257 #define CONFIG_SYS_FLASH_WRITE_TOUT     (100 * CONFIG_SYS_HZ)
 258
 259 /* Flash banks JFFS2 should use */
 260 #define CONFIG_SYS_MAX_MTD_BANKS        (CONFIG_SYS_MAX_FLASH_BANKS + \
 261                                         CONFIG_SYS_MAX_NAND_DEVICE)
 262 #define CONFIG_SYS_JFFS2_MEM_NAND
 263 /* use flash_info[2] */
 264 #define CONFIG_SYS_JFFS2_FIRST_BANK     CONFIG_SYS_MAX_FLASH_BANKS
 265 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 266
 267 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 268 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 269 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 270 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 271                                          CONFIG_SYS_INIT_RAM_SIZE - \
 272                                          GENERATED_GBL_DATA_SIZE)
 273
 274 /* Defines for SPL */
 275 #define CONFIG_SPL_FRAMEWORK
 276 #define CONFIG_SPL_BOARD_INIT
 277 #define CONFIG_SPL_NAND_SIMPLE
 278 #define CONFIG_SPL_TEXT_BASE            0x40200800
 279 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 280                                          CONFIG_SPL_TEXT_BASE)
 281
 282 #define CONFIG_SPL_BSS_START_ADDR       0x80000000
 283 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 284
 285 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 286 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      0x200 /* 256 KB */
 287 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 288 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 289
 290 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 291 #define CONFIG_SPL_LIBDISK_SUPPORT
 292 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 293 #define CONFIG_SPL_MMC_SUPPORT
 294 #define CONFIG_SPL_SERIAL_SUPPORT
 295 #define CONFIG_SPL_NAND_SUPPORT
 296 #define CONFIG_SPL_NAND_BASE
 297 #define CONFIG_SPL_NAND_DRIVERS
 298 #define CONFIG_SPL_NAND_ECC
 299 #define CONFIG_SPL_POWER_SUPPORT
 300 #define CONFIG_SPL_LDSCRIPT             "$(CPUDIR)/omap-common/u-boot-spl.lds"
 301
 302 /* NAND boot config */
 303 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
 304 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 305 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 306 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 307 #define CONFIG_SYS_NAND_OOBSIZE         64
 308 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 309 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 310 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
 311                                                 10, 11, 12, 13}
 312 #define CONFIG_SYS_NAND_ECCSIZE         512
 313 #define CONFIG_SYS_NAND_ECCBYTES        3
 314 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 315 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 316 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 317
 318 /*
 319  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 320  * 64 bytes before this address should be set aside for u-boot.img's
 321  * header. That is 0x800FFFC0--0x80100000 should not be used for any
 322  * other needs.
 323  */
 324 #define CONFIG_SYS_TEXT_BASE            0x80100000
 325 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 326 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 327
 328 #endif /* __CONFIG_H */