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1 /*
2 *
3 * Configuration settings for the Armadeus Project motherboard APF27
4 *
5 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 #define CONFIG_ENV_VERSION 10
14 #define CONFIG_BOARD_NAME apf27
15
16 /*
17 * SoC configurations
18 */
19 #define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */
20 #define CONFIG_MACH_TYPE 1698 /* APF27 */
21
22 /*
23 * Enable the call to miscellaneous platform dependent initialization.
24 */
25 #define CONFIG_SYS_NO_FLASH
26
27 /*
28 * Board display option
29 */
30 #define CONFIG_DISPLAY_BOARDINFO
31
32 /*
33 * SPL
34 */
35 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
36 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
37 #define CONFIG_SPL_MAX_SIZE 2048
38 #define CONFIG_SPL_TEXT_BASE 0xA0000000
39
40 /* NAND boot config */
41 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
42 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
43 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
44 #define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800
45
46 /*
47 * BOOTP options
48 */
49 #define CONFIG_BOOTP_SUBNETMASK
50 #define CONFIG_BOOTP_GATEWAY
51 #define CONFIG_BOOTP_HOSTNAME
52 #define CONFIG_BOOTP_BOOTPATH
53 #define CONFIG_BOOTP_BOOTFILESIZE
54 #define CONFIG_BOOTP_DNS
55 #define CONFIG_BOOTP_DNS2
56
57 #define CONFIG_HOSTNAME CONFIG_BOARD_NAME
58 #define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
59
60 /*
61 * U-Boot Commands
62 */
63 #define CONFIG_CMD_BSP /* Board Specific functions */
64 #define CONFIG_CMD_DATE
65 #define CONFIG_CMD_EEPROM
66 #define CONFIG_CMD_IMX_FUSE /* imx iim fuse */
67 #define CONFIG_CMD_MTDPARTS /* MTD partition support */
68 #define CONFIG_CMD_NAND /* NAND support */
69 #define CONFIG_CMD_NAND_LOCK_UNLOCK
70 #define CONFIG_CMD_NAND_TRIMFFS
71 #define CONFIG_CMD_UBIFS
72
73 /*
74 * Memory configurations
75 */
76 #define CONFIG_NR_DRAM_POPULATED 1
77 #define CONFIG_NR_DRAM_BANKS 2
78
79 #define ACFG_SDRAM_MBYTE_SYZE 64
80
81 #define PHYS_SDRAM_1 0xA0000000
82 #define PHYS_SDRAM_2 0xB0000000
83 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
84 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10))
85 #define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */
86 #define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */
87
88 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
89 + PHYS_SDRAM_1_SIZE - 0x0100000)
90
91 #define CONFIG_SYS_TEXT_BASE 0xA0000800
92
93 /*
94 * FLASH organization
95 */
96 #define ACFG_MONITOR_OFFSET 0x00000000
97 #define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */
98 #define CONFIG_ENV_IS_IN_NAND
99 #define CONFIG_ENV_OVERWRITE
100 #define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */
101 #define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
102 #define CONFIG_ENV_RANGE 0X00080000 /* 512kB */
103 #define CONFIG_ENV_OFFSET_REDUND \
104 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */
105 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */
106 #define CONFIG_FIRMWARE_OFFSET 0x00200000
107 #define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */
108 #define CONFIG_KERNEL_OFFSET 0x00300000
109 #define CONFIG_ROOTFS_OFFSET 0x00800000
110
111 #define CONFIG_MTDMAP "mxc_nand.0"
112 #define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP
113 #define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \
114 ":1M(u-boot)ro," \
115 "512K(env)," \
116 "512K(env2)," \
117 "512K(firmware)," \
118 "512K(dtb)," \
119 "5M(kernel)," \
120 "-(rootfs)"
121
122 /*
123 * U-Boot general configurations
124 */
125 #define CONFIG_SYS_LONGHELP
126 #define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
127 #define CONFIG_SYS_PBSIZE \
128 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
129 /* Print buffer size */
130 #define CONFIG_SYS_MAXARGS 16 /* max command args */
131 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
132 /* Boot argument buffer size */
133 #define CONFIG_AUTO_COMPLETE
134 #define CONFIG_CMDLINE_EDITING
135 #define CONFIG_ENV_VARS_UBOOT_CONFIG
136 #define CONFIG_PREBOOT "run check_flash check_env;"
137
138 /*
139 * Boot Linux
140 */
141 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
142 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
143 #define CONFIG_INITRD_TAG /* send initrd params */
144
145 #define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin"
146 #define CONFIG_BOOTARGS "console=" __stringify(ACFG_CONSOLE_DEV) "," \
147 __stringify(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \
148 " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs "
149
150 #define ACFG_CONSOLE_DEV ttySMX0
151 #define CONFIG_BOOTCOMMAND "run ubifsboot"
152 #define CONFIG_SYS_AUTOLOAD "no"
153 /*
154 * Default load address for user programs and kernel
155 */
156 #define CONFIG_LOADADDR 0xA0000000
157 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
158
159 /*
160 * Extra Environments
161 */
162 #define CONFIG_EXTRA_ENV_SETTINGS \
163 "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \
164 "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \
165 "mtdparts=" MTDPARTS_DEFAULT "\0" \
166 "partition=nand0,6\0" \
167 "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \
168 "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \
169 "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \
170 "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \
171 "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \
172 "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \
173 "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \
174 "kernel_addr_r=A0000000\0" \
175 "check_env=if test -n ${flash_env_version}; " \
176 "then env default env_version; " \
177 "else env set flash_env_version ${env_version}; env save; "\
178 "fi; " \
179 "if itest ${flash_env_version} < ${env_version}; then " \
180 "echo \"*** Warning - Environment version" \
181 " change suggests: run flash_reset_env; reset\"; "\
182 "env default flash_reset_env; "\
183 "fi; \0" \
184 "check_flash=nand lock; nand unlock ${env_addr}; \0" \
185 "flash_reset_env=env default -f -a; saveenv; run update_env;" \
186 "echo Flash environment variables erased!\0" \
187 "download_uboot=tftpboot ${loadaddr} ${board_name}" \
188 "-u-boot-with-spl.bin\0" \
189 "flash_uboot=nand unlock ${u-boot_addr} ;" \
190 "nand erase.part u-boot;" \
191 "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
192 "then nand lock; nand unlock ${env_addr};" \
193 "echo Flashing of uboot succeed;" \
194 "else echo Flashing of uboot failed;" \
195 "fi; \0" \
196 "update_uboot=run download_uboot flash_uboot\0" \
197 "download_env=tftpboot ${loadaddr} ${board_name}" \
198 "-u-boot-env.txt\0" \
199 "flash_env=env import -t ${loadaddr}; env save; \0" \
200 "update_env=run download_env flash_env\0" \
201 "update_all=run update_env update_uboot\0" \
202 "unlock_regs=mw 10000008 0; mw 10020008 0\0" \
203
204 /*
205 * Serial Driver
206 */
207 #define CONFIG_MXC_UART
208 #define CONFIG_CONS_INDEX 1
209 #define CONFIG_BAUDRATE 115200
210 #define CONFIG_MXC_UART_BASE UART1_BASE
211
212 /*
213 * GPIO
214 */
215 #define CONFIG_MXC_GPIO
216
217 /*
218 * NOR
219 */
220
221 /*
222 * NAND
223 */
224 #define CONFIG_NAND_MXC
225
226 #define CONFIG_MXC_NAND_REGS_BASE 0xD8000000
227 #define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE
228 #define CONFIG_SYS_MAX_NAND_DEVICE 1
229
230 #define CONFIG_MXC_NAND_HWECC
231 #define CONFIG_SYS_NAND_LARGEPAGE
232 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
233 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
234 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
235 #define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \
236 CONFIG_SYS_NAND_PAGE_SIZE
237 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
238 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 11
239 #define NAND_MAX_CHIPS 1
240
241 #define CONFIG_FLASH_SHOW_PROGRESS 45
242 #define CONFIG_SYS_NAND_QUIET 1
243
244 /*
245 * Partitions & Filsystems
246 */
247 #define CONFIG_MTD_DEVICE
248 #define CONFIG_MTD_PARTITIONS
249 #define CONFIG_DOS_PARTITION
250 #define CONFIG_SUPPORT_VFAT
251
252 /*
253 * UBIFS
254 */
255 #define CONFIG_RBTREE
256 #define CONFIG_LZO
257
258 /*
259 * Ethernet (on SOC imx FEC)
260 */
261 #define CONFIG_FEC_MXC
262 #define CONFIG_FEC_MXC_PHYADDR 0x1f
263 #define CONFIG_MII /* MII PHY management */
264
265 /*
266 * FPGA
267 */
268 #ifndef CONFIG_SPL_BUILD
269 #define CONFIG_FPGA
270 #endif
271 #define CONFIG_FPGA_COUNT 1
272 #define CONFIG_FPGA_XILINX
273 #define CONFIG_FPGA_SPARTAN3
274 #define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */
275 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
276 #define CONFIG_SYS_FPGA_CHECK_CTRLC
277 #define CONFIG_SYS_FPGA_CHECK_ERROR
278
279 /*
280 * Fuses - IIM
281 */
282 #ifdef CONFIG_CMD_IMX_FUSE
283 #define IIM_MAC_BANK 0
284 #define IIM_MAC_ROW 5
285 #define IIM0_SCC_KEY 11
286 #define IIM1_SUID 1
287 #endif
288
289 /*
290 * I2C
291 */
292
293 #ifdef CONFIG_CMD_I2C
294 #define CONFIG_SYS_I2C
295 #define CONFIG_SYS_I2C_MXC
296 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
297 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
298 #define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */
299 #define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F
300 #define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */
301 #define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F
302 #define CONFIG_SYS_I2C_NOPROBES { }
303
304 #ifdef CONFIG_CMD_EEPROM
305 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
306 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
307 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
308 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */
309 #endif /* CONFIG_CMD_EEPROM */
310 #endif /* CONFIG_CMD_I2C */
311
312 /*
313 * SD/MMC
314 */
315 #ifdef CONFIG_CMD_MMC
316 #define CONFIG_MMC
317 #define CONFIG_GENERIC_MMC
318 #define CONFIG_MXC_MMC
319 #define CONFIG_MXC_MCI_REGS_BASE 0x10014000
320 #endif
321
322 /*
323 * RTC
324 */
325 #ifdef CONFIG_CMD_DATE
326 #define CONFIG_RTC_DS1374
327 #define CONFIG_SYS_RTC_BUS_NUM 0
328 #endif /* CONFIG_CMD_DATE */
329
330 /*
331 * PLL
332 *
333 * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
334 * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
335 */
336 #define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */
337
338 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
339 /* micron 64MB */
340 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
341 #define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
342 #endif
343
344 #if (ACFG_SDRAM_MBYTE_SYZE == 128)
345 /* micron 128MB */
346 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
347 #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
348 #endif
349
350 #if (ACFG_SDRAM_MBYTE_SYZE == 256)
351 /* micron 256MB */
352 #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
353 #define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */
354 #endif
355
356 #endif /* __CONFIG_H */