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1 /*
2 *
3 * Configuration settings for the Armadeus Project motherboard APF27
4 *
5 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 #define CONFIG_ENV_VERSION 10
14 #define CONFIG_IDENT_STRING " apf27 patch 3.10"
15 #define CONFIG_BOARD_NAME apf27
16
17 /*
18 * SoC configurations
19 */
20 #define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */
21 #define CONFIG_MACH_TYPE 1698 /* APF27 */
22
23 /*
24 * Enable the call to miscellaneous platform dependent initialization.
25 */
26 #define CONFIG_SYS_NO_FLASH
27
28 /*
29 * Board display option
30 */
31 #define CONFIG_DISPLAY_BOARDINFO
32 #define CONFIG_DISPLAY_CPUINFO
33
34 /*
35 * SPL
36 */
37 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
38 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
39 #define CONFIG_SPL_MAX_SIZE 2048
40 #define CONFIG_SPL_TEXT_BASE 0xA0000000
41
42 /* NAND boot config */
43 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
44 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
45 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
46 #define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800
47
48 /*
49 * BOOTP options
50 */
51 #define CONFIG_BOOTP_SUBNETMASK
52 #define CONFIG_BOOTP_GATEWAY
53 #define CONFIG_BOOTP_HOSTNAME
54 #define CONFIG_BOOTP_BOOTPATH
55 #define CONFIG_BOOTP_BOOTFILESIZE
56 #define CONFIG_BOOTP_DNS
57 #define CONFIG_BOOTP_DNS2
58
59 #define CONFIG_HOSTNAME CONFIG_BOARD_NAME
60 #define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
61
62 /*
63 * U-Boot Commands
64 */
65 #define CONFIG_CMD_BSP /* Board Specific functions */
66 #define CONFIG_CMD_DATE
67 #define CONFIG_CMD_EEPROM
68 #define CONFIG_CMD_IMX_FUSE /* imx iim fuse */
69 #define CONFIG_CMD_MTDPARTS /* MTD partition support */
70 #define CONFIG_CMD_NAND /* NAND support */
71 #define CONFIG_CMD_NAND_LOCK_UNLOCK
72 #define CONFIG_CMD_NAND_TRIMFFS
73 #define CONFIG_CMD_UBI
74 #define CONFIG_CMD_UBIFS
75
76 /*
77 * Memory configurations
78 */
79 #define CONFIG_NR_DRAM_POPULATED 1
80 #define CONFIG_NR_DRAM_BANKS 2
81
82 #define ACFG_SDRAM_MBYTE_SYZE 64
83
84 #define PHYS_SDRAM_1 0xA0000000
85 #define PHYS_SDRAM_2 0xB0000000
86 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
87 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10))
88 #define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */
89 #define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */
90
91 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
92 + PHYS_SDRAM_1_SIZE - 0x0100000)
93
94 #define CONFIG_SYS_TEXT_BASE 0xA0000800
95
96 /*
97 * FLASH organization
98 */
99 #define ACFG_MONITOR_OFFSET 0x00000000
100 #define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */
101 #define CONFIG_ENV_IS_IN_NAND
102 #define CONFIG_ENV_OVERWRITE
103 #define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */
104 #define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
105 #define CONFIG_ENV_RANGE 0X00080000 /* 512kB */
106 #define CONFIG_ENV_OFFSET_REDUND \
107 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */
108 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */
109 #define CONFIG_FIRMWARE_OFFSET 0x00200000
110 #define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */
111 #define CONFIG_KERNEL_OFFSET 0x00300000
112 #define CONFIG_ROOTFS_OFFSET 0x00800000
113
114 #define CONFIG_MTDMAP "mxc_nand.0"
115 #define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP
116 #define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \
117 ":1M(u-boot)ro," \
118 "512K(env)," \
119 "512K(env2)," \
120 "512K(firmware)," \
121 "512K(dtb)," \
122 "5M(kernel)," \
123 "-(rootfs)"
124
125 /*
126 * U-Boot general configurations
127 */
128 #define CONFIG_SYS_LONGHELP
129 #define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
130 #define CONFIG_SYS_PBSIZE \
131 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
132 /* Print buffer size */
133 #define CONFIG_SYS_MAXARGS 16 /* max command args */
134 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
135 /* Boot argument buffer size */
136 #define CONFIG_AUTO_COMPLETE
137 #define CONFIG_CMDLINE_EDITING
138 #define CONFIG_ENV_VARS_UBOOT_CONFIG
139 #define CONFIG_PREBOOT "run check_flash check_env;"
140
141 /*
142 * Boot Linux
143 */
144 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
145 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
146 #define CONFIG_INITRD_TAG /* send initrd params */
147
148 #define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin"
149 #define CONFIG_BOOTARGS "console=" __stringify(ACFG_CONSOLE_DEV) "," \
150 __stringify(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \
151 " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs "
152
153 #define ACFG_CONSOLE_DEV ttySMX0
154 #define CONFIG_BOOTCOMMAND "run ubifsboot"
155 #define CONFIG_SYS_AUTOLOAD "no"
156 /*
157 * Default load address for user programs and kernel
158 */
159 #define CONFIG_LOADADDR 0xA0000000
160 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
161
162 /*
163 * Extra Environments
164 */
165 #define CONFIG_EXTRA_ENV_SETTINGS \
166 "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \
167 "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \
168 "mtdparts=" MTDPARTS_DEFAULT "\0" \
169 "partition=nand0,6\0" \
170 "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \
171 "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \
172 "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \
173 "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \
174 "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \
175 "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \
176 "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \
177 "kernel_addr_r=A0000000\0" \
178 "check_env=if test -n ${flash_env_version}; " \
179 "then env default env_version; " \
180 "else env set flash_env_version ${env_version}; env save; "\
181 "fi; " \
182 "if itest ${flash_env_version} < ${env_version}; then " \
183 "echo \"*** Warning - Environment version" \
184 " change suggests: run flash_reset_env; reset\"; "\
185 "env default flash_reset_env; "\
186 "fi; \0" \
187 "check_flash=nand lock; nand unlock ${env_addr}; \0" \
188 "flash_reset_env=env default -f -a; saveenv; run update_env;" \
189 "echo Flash environment variables erased!\0" \
190 "download_uboot=tftpboot ${loadaddr} ${board_name}" \
191 "-u-boot-with-spl.bin\0" \
192 "flash_uboot=nand unlock ${u-boot_addr} ;" \
193 "nand erase.part u-boot;" \
194 "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
195 "then nand lock; nand unlock ${env_addr};" \
196 "echo Flashing of uboot succeed;" \
197 "else echo Flashing of uboot failed;" \
198 "fi; \0" \
199 "update_uboot=run download_uboot flash_uboot\0" \
200 "download_env=tftpboot ${loadaddr} ${board_name}" \
201 "-u-boot-env.txt\0" \
202 "flash_env=env import -t ${loadaddr}; env save; \0" \
203 "update_env=run download_env flash_env\0" \
204 "update_all=run update_env update_uboot\0" \
205 "unlock_regs=mw 10000008 0; mw 10020008 0\0" \
206
207 /*
208 * Serial Driver
209 */
210 #define CONFIG_MXC_UART
211 #define CONFIG_CONS_INDEX 1
212 #define CONFIG_BAUDRATE 115200
213 #define CONFIG_MXC_UART_BASE UART1_BASE
214
215 /*
216 * GPIO
217 */
218 #define CONFIG_MXC_GPIO
219
220 /*
221 * NOR
222 */
223
224 /*
225 * NAND
226 */
227 #define CONFIG_NAND_MXC
228
229 #define CONFIG_MXC_NAND_REGS_BASE 0xD8000000
230 #define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE
231 #define CONFIG_SYS_MAX_NAND_DEVICE 1
232
233 #define CONFIG_MXC_NAND_HWECC
234 #define CONFIG_SYS_NAND_LARGEPAGE
235 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
236 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
237 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
238 #define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \
239 CONFIG_SYS_NAND_PAGE_SIZE
240 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
241 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 11
242 #define NAND_MAX_CHIPS 1
243
244 #define CONFIG_FLASH_SHOW_PROGRESS 45
245 #define CONFIG_SYS_NAND_QUIET 1
246
247 /*
248 * Partitions & Filsystems
249 */
250 #define CONFIG_MTD_DEVICE
251 #define CONFIG_MTD_PARTITIONS
252 #define CONFIG_DOS_PARTITION
253 #define CONFIG_SUPPORT_VFAT
254
255 /*
256 * UBIFS
257 */
258 #define CONFIG_RBTREE
259 #define CONFIG_LZO
260
261 /*
262 * Ethernet (on SOC imx FEC)
263 */
264 #define CONFIG_FEC_MXC
265 #define CONFIG_FEC_MXC_PHYADDR 0x1f
266 #define CONFIG_MII /* MII PHY management */
267
268 /*
269 * FPGA
270 */
271 #ifndef CONFIG_SPL_BUILD
272 #define CONFIG_FPGA
273 #endif
274 #define CONFIG_FPGA_COUNT 1
275 #define CONFIG_FPGA_XILINX
276 #define CONFIG_FPGA_SPARTAN3
277 #define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */
278 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
279 #define CONFIG_SYS_FPGA_CHECK_CTRLC
280 #define CONFIG_SYS_FPGA_CHECK_ERROR
281
282 /*
283 * Fuses - IIM
284 */
285 #ifdef CONFIG_CMD_IMX_FUSE
286 #define IIM_MAC_BANK 0
287 #define IIM_MAC_ROW 5
288 #define IIM0_SCC_KEY 11
289 #define IIM1_SUID 1
290 #endif
291
292 /*
293 * I2C
294 */
295
296 #ifdef CONFIG_CMD_I2C
297 #define CONFIG_SYS_I2C
298 #define CONFIG_SYS_I2C_MXC
299 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
300 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
301 #define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */
302 #define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F
303 #define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */
304 #define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F
305 #define CONFIG_SYS_I2C_NOPROBES { }
306
307 #ifdef CONFIG_CMD_EEPROM
308 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
309 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
310 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
311 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */
312 #endif /* CONFIG_CMD_EEPROM */
313 #endif /* CONFIG_CMD_I2C */
314
315 /*
316 * SD/MMC
317 */
318 #ifdef CONFIG_CMD_MMC
319 #define CONFIG_MMC
320 #define CONFIG_GENERIC_MMC
321 #define CONFIG_MXC_MMC
322 #define CONFIG_MXC_MCI_REGS_BASE 0x10014000
323 #endif
324
325 /*
326 * RTC
327 */
328 #ifdef CONFIG_CMD_DATE
329 #define CONFIG_RTC_DS1374
330 #define CONFIG_SYS_RTC_BUS_NUM 0
331 #endif /* CONFIG_CMD_DATE */
332
333 /*
334 * PLL
335 *
336 * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
337 * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
338 */
339 #define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */
340
341 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
342 /* micron 64MB */
343 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
344 #define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
345 #endif
346
347 #if (ACFG_SDRAM_MBYTE_SYZE == 128)
348 /* micron 128MB */
349 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
350 #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
351 #endif
352
353 #if (ACFG_SDRAM_MBYTE_SYZE == 256)
354 /* micron 256MB */
355 #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
356 #define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */
357 #endif
358
359 #endif /* __CONFIG_H */