include/configs/astro_mcf5373l.h

   1 /*
   2  * Configuration settings for the Sentec Cobra Board.
   3  *
   4  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * configuration for ASTRO "Urmel" board.
  11  * Originating from Cobra5272 configuration, messed up by
  12  * Wolfgang Wegner <w.wegner@astro-kom.de>
  13  * Please do not bother the original author with bug reports
  14  * concerning this file.
  15  */
  16
  17 #ifndef _CONFIG_ASTRO_MCF5373L_H
  18 #define _CONFIG_ASTRO_MCF5373L_H
  19
  20 #include <linux/stringify.h>
  21
  22 /*
  23  * set the card type to actually compile for; either of
  24  * the possibilities listed below has to be used!
  25  */
  26 #define CONFIG_ASTRO_V532       1
  27
  28 #if CONFIG_ASTRO_V532
  29 #define ASTRO_ID        0xF8
  30 #elif CONFIG_ASTRO_V512
  31 #define ASTRO_ID        0xFA
  32 #elif CONFIG_ASTRO_TWIN7S2
  33 #define ASTRO_ID        0xF9
  34 #elif CONFIG_ASTRO_V912
  35 #define ASTRO_ID        0xFC
  36 #elif CONFIG_ASTRO_COFDMDUOS2
  37 #define ASTRO_ID        0xFB
  38 #else
  39 #error No card type defined!
  40 #endif
  41
  42 #define CONFIG_ASTRO5373L               /* define board type */
  43
  44 /* Command line configuration */
  45 /*
  46  * CONFIG_RAM defines if u-boot is loaded via BDM (or started from
  47  * a different bootloader that has already performed RAM setup) or
  48  * started directly from flash, which is the regular case for production
  49  * boards.
  50  */
  51 #ifdef CONFIG_RAM
  52 #define CONFIG_MONITOR_IS_IN_RAM
  53 #define CONFIG_SYS_TEXT_BASE            0x40020000
  54 #define ENABLE_JFFS     0
  55 #else
  56 #define CONFIG_SYS_TEXT_BASE            0x00000000
  57 #define ENABLE_JFFS     1
  58 #endif
  59
  60 /* Define which commands should be available at u-boot command prompt */
  61
  62 #define CONFIG_CMD_CACHE
  63 #define CONFIG_CMD_DATE
  64 #if ENABLE_JFFS
  65 #define CONFIG_CMD_JFFS2
  66 #endif
  67 #define CONFIG_CMD_REGINFO
  68 #define CONFIG_CMD_FPGA_LOADMK
  69 #define CONFIG_CMDLINE_EDITING
  70
  71 #define CONFIG_MCFRTC
  72 #undef RTC_DEBUG
  73
  74 /* Timer */
  75 #define CONFIG_MCFTMR
  76 #undef CONFIG_MCFPIT
  77
  78 /* I2C */
  79 #define CONFIG_SYS_I2C
  80 #define CONFIG_SYS_I2C_FSL
  81 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  82 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  83 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
  84 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
  85
  86 /*
  87  * Defines processor clock - important for correct timings concerning serial
  88  * interface etc.
  89  */
  90
  91 #define CONFIG_SYS_CLK                  80000000
  92 #define CONFIG_SYS_CPU_CLK              (CONFIG_SYS_CLK * 3)
  93 #define CONFIG_SYS_SDRAM_SIZE           32              /* SDRAM size in MB */
  94
  95 #define CONFIG_SYS_CORE_SRAM_SIZE       0x8000
  96 #define CONFIG_SYS_CORE_SRAM            0x80000000
  97
  98 #define CONFIG_SYS_UNIFY_CACHE
  99
 100 /*
 101  * Define baudrate for UART1 (console output, tftp, ...)
 102  * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
 103  * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected
 104  * in u-boot command interface
 105  */
 106
 107 #define CONFIG_BAUDRATE         115200
 108
 109 #define CONFIG_MCFUART
 110 #define CONFIG_SYS_UART_PORT            (2)
 111 #define CONFIG_SYS_UART2_ALT3_GPIO
 112
 113 /*
 114  * Watchdog configuration; Watchdog is disabled for running from RAM
 115  * and set to highest possible value else. Beware there is no check
 116  * in the watchdog code to validate the timeout value set here!
 117  */
 118
 119 #ifndef CONFIG_MONITOR_IS_IN_RAM
 120 #define CONFIG_WATCHDOG
 121 #define CONFIG_WATCHDOG_TIMEOUT 3355    /* timeout in milliseconds */
 122 #endif
 123
 124 /*
 125  * Configuration for environment
 126  * Environment is located in the last sector of the flash
 127  */
 128
 129 #ifndef CONFIG_MONITOR_IS_IN_RAM
 130 #define CONFIG_ENV_OFFSET               0x1FF8000
 131 #define CONFIG_ENV_SECT_SIZE            0x8000
 132 #define CONFIG_ENV_IS_IN_FLASH          1
 133 #else
 134 /*
 135  * environment in RAM - This is used to use a single PC-based application
 136  * to load an image, load U-Boot, load an environment and then start U-Boot
 137  * to execute the commands from the environment. Feedback is done via setting
 138  * and reading memory locations.
 139  */
 140 #define CONFIG_ENV_ADDR         0x40060000
 141 #define CONFIG_ENV_SECT_SIZE    0x8000
 142 #define CONFIG_ENV_IS_IN_FLASH  1
 143 #endif
 144
 145 /* here we put our FPGA configuration... */
 146 #define CONFIG_MISC_INIT_R      1
 147
 148 /* Define user parameters that have to be customized most likely */
 149
 150 /* AUTOBOOT settings - booting images automatically by u-boot after power on */
 151
 152 /*
 153  * used for autoboot, delay in seconds u-boot will wait before starting
 154  * defined (auto-)boot command, setting to -1 disables delay, setting to
 155  * 0 will too prevent access to u-boot command interface: u-boot then has
 156  * to be reflashed
 157  * beware - watchdog is not serviced during autoboot delay time!
 158  */
 159 #ifdef CONFIG_MONITOR_IS_IN_RAM
 160 #define CONFIG_BOOTDELAY        1
 161 #else
 162 #define CONFIG_BOOTDELAY        1
 163 #endif
 164
 165 /*
 166  * The following settings will be contained in the environment block ; if you
 167  * want to use a neutral environment all those settings can be manually set in
 168  * u-boot: 'set' command
 169  */
 170
 171 #define CONFIG_EXTRA_ENV_SETTINGS                       \
 172         "loaderversion=11\0"                            \
 173         "card_id="__stringify(ASTRO_ID)"\0"                     \
 174         "alterafile=0\0"                                \
 175         "xilinxfile=0\0"                                \
 176         "xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\
 177                 "fpga load 0 0x41000000 $filesize\0" \
 178         "alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\
 179                 "fpga load 1 0x41000000 $filesize\0" \
 180         "env_default=1\0"                               \
 181         "env_check=if test $env_default -eq 1;"\
 182                 " then setenv env_default 0;saveenv;fi\0"
 183
 184 /*
 185  * "update" is a non-standard command that has to be supplied
 186  * by external update.c; This is not included in mainline because
 187  * it needs non-blocking CFI routines.
 188  */
 189 #ifdef CONFIG_MONITOR_IS_IN_RAM
 190 #define CONFIG_BOOTCOMMAND      ""      /* no autoboot in this case */
 191 #else
 192 #if CONFIG_ASTRO_V532
 193 #define CONFIG_BOOTCOMMAND      "protect off 0x80000 0x1ffffff;run env_check;"\
 194                                 "run xilinxload&&run alteraload&&bootm 0x80000;"\
 195                                 "update;reset"
 196 #else
 197 #define CONFIG_BOOTCOMMAND      "protect off 0x80000 0x1ffffff;run env_check;"\
 198                                 "run xilinxload&&bootm 0x80000;update;reset"
 199 #endif
 200 #endif
 201
 202 /* default bootargs that are considered during boot */
 203 #define CONFIG_BOOTARGS         " console=ttyS2,115200 rootfstype=romfs"\
 204                                 " loaderversion=$loaderversion"
 205
 206 /* default RAM address for user programs */
 207 #define CONFIG_SYS_LOAD_ADDR    0x20000
 208
 209 #define CONFIG_SYS_LONGHELP
 210
 211 #if (CONFIG_COMMANDS & CONFIG_CMD_KGDB)
 212 #define CONFIG_SYS_CBSIZE               1024
 213 #else
 214 #define CONFIG_SYS_CBSIZE               256
 215 #endif
 216 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 217 #define CONFIG_SYS_MAXARGS              16
 218 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 219
 220 #define CONFIG_FPGA_COUNT       1
 221 #define CONFIG_FPGA
 222 #define CONFIG_FPGA_XILINX
 223 #define CONFIG_FPGA_SPARTAN3
 224 #define CONFIG_FPGA_ALTERA
 225 #define CONFIG_FPGA_CYCLON2
 226 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 227 #define CONFIG_SYS_FPGA_WAIT            1000
 228
 229 /* End of user parameters to be customized */
 230
 231 /* Defines memory range for test */
 232
 233 #define CONFIG_SYS_MEMTEST_START        0x40020000
 234 #define CONFIG_SYS_MEMTEST_END          0x41ffffff
 235
 236 /*
 237  * Low Level Configuration Settings
 238  * (address mappings, register initial values, etc.)
 239  * You should know what you are doing if you make changes here.
 240  */
 241
 242 /* Base register address */
 243
 244 #define CONFIG_SYS_MBAR         0xFC000000      /* Register Base Addrs */
 245
 246 /* System Conf. Reg. & System Protection Reg. */
 247
 248 #define CONFIG_SYS_SCR          0x0003;
 249 #define CONFIG_SYS_SPR          0xffff;
 250
 251 /*
 252  * Definitions for initial stack pointer and data area (in internal SRAM)
 253  */
 254 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 255 #define CONFIG_SYS_INIT_RAM_SIZE                0x8000
 256 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 257 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 258                                          GENERATED_GBL_DATA_SIZE)
 259 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 260
 261 /*
 262  * Start addresses for the final memory configuration
 263  * (Set up by the startup code)
 264  * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000
 265  */
 266 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 267
 268 /*
 269  * Chipselect bank definitions
 270  *
 271  * CS0 - Flash 32MB (first 16MB)
 272  * CS1 - Flash 32MB (second half)
 273  * CS2 - FPGA
 274  * CS3 - FPGA
 275  * CS4 - unused
 276  * CS5 - unused
 277  */
 278 #define CONFIG_SYS_CS0_BASE             0
 279 #define CONFIG_SYS_CS0_MASK             0x00ff0001
 280 #define CONFIG_SYS_CS0_CTRL             0x00001fc0
 281
 282 #define CONFIG_SYS_CS1_BASE             0x01000000
 283 #define CONFIG_SYS_CS1_MASK             0x00ff0001
 284 #define CONFIG_SYS_CS1_CTRL             0x00001fc0
 285
 286 #define CONFIG_SYS_CS2_BASE             0x20000000
 287 #define CONFIG_SYS_CS2_MASK             0x00ff0001
 288 #define CONFIG_SYS_CS2_CTRL             0x0000fec0
 289
 290 #define CONFIG_SYS_CS3_BASE             0x21000000
 291 #define CONFIG_SYS_CS3_MASK             0x00ff0001
 292 #define CONFIG_SYS_CS3_CTRL             0x0000fec0
 293
 294 #define CONFIG_SYS_FLASH_BASE           0x00000000
 295
 296 #ifdef  CONFIG_MONITOR_IS_IN_RAM
 297 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 298 #else
 299 /* This is mainly used during relocation in start.S */
 300 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_FLASH_BASE + 0x400)
 301 #endif
 302 /* Reserve 256 kB for Monitor */
 303 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)
 304
 305 #define CONFIG_SYS_BOOTPARAMS_LEN       (64 * 1024)
 306 /* Reserve 128 kB for malloc() */
 307 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)
 308
 309 /*
 310  * For booting Linux, the board info and command line data
 311  * have to be in the first 8 MB of memory, since this is
 312  * the maximum mapped by the Linux kernel during initialization ??
 313  */
 314 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + \
 315                                                 (CONFIG_SYS_SDRAM_SIZE << 20))
 316
 317 /* FLASH organization */
 318 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 319 #define CONFIG_SYS_MAX_FLASH_SECT       259
 320 #define CONFIG_SYS_FLASH_ERASE_TOUT     1000
 321
 322 #define CONFIG_SYS_FLASH_CFI            1
 323 #define CONFIG_FLASH_CFI_DRIVER         1
 324 #define CONFIG_SYS_FLASH_SIZE           0x2000000
 325 #define CONFIG_SYS_FLASH_PROTECTION     1
 326 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 327 #define CONFIG_SYS_FLASH_CFI_NONBLOCK   1
 328
 329 #define LDS_BOARD_TEXT \
 330         . = DEFINED(env_offset) ? env_offset : .; \
 331         common/env_embedded.o       (.text*)
 332
 333 #if ENABLE_JFFS
 334 /* JFFS Partition offset set */
 335 #define CONFIG_SYS_JFFS2_FIRST_BANK    0
 336 #define CONFIG_SYS_JFFS2_NUM_BANKS     1
 337 /* 512k reserved for u-boot */
 338 #define CONFIG_SYS_JFFS2_FIRST_SECTOR  0x40
 339 #endif
 340
 341 /* Cache Configuration */
 342 #define CONFIG_SYS_CACHELINE_SIZE       16
 343
 344 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 345                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 346 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 347                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 348 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
 349 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 350                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 351                                          CF_ACR_EN | CF_ACR_SM_ALL)
 352 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_EC | CF_CACR_CINVA | \
 353                                          CF_CACR_DCM_P)
 354
 355 #endif  /* _CONFIG_ASTRO_MCF5373L_H */