include/configs/at91rm9200dk.h

   1 /*
   2  * Rick Bronson <rick@efn.org>
   3  *
   4  * Configuation settings for the AT91RM9200DK board.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 /* ARM asynchronous clock */
  29 #define AT91C_MAIN_CLOCK  179712000  /* from 18.432 MHz crystal (18432000 / 4 * 39) */
  30 #define AT91C_MASTER_CLOCK  59904000  /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
  31 /* #define AT91C_MASTER_CLOCK  44928000 */  /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
  32
  33 #define CONFIG_AT91RM9200DK      1      /* on an AT91RM9200DK Board      */
  34 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
  35 #define CONFIG_CMDLINE_TAG       1      /* enable passing of ATAGs      */
  36 #define CONFIG_SETUP_MEMORY_TAGS 1
  37 #define CONFIG_INITRD_TAG        1
  38
  39 /*
  40  * Size of malloc() pool
  41  */
  42 #define CFG_MALLOC_LEN  (CFG_ENV_SIZE + 128*1024)
  43 #define CONFIG_BAUDRATE 115200
  44 /*
  45  * Hardware drivers
  46  */
  47
  48 #undef  CONFIG_HWFLOW                   /* don't include RTS/CTS flow control support   */
  49
  50 #undef  CONFIG_MODEM_SUPPORT            /* disable modem initialization stuff */
  51
  52 #define CONFIG_BOOTDELAY      3
  53 /* #define CONFIG_ENV_OVERWRITE  1 */
  54
  55 #define CONFIG_COMMANDS         \
  56                        ((CONFIG_CMD_DFL | \
  57                         CFG_CMD_DHCP ) & \
  58                       ~(CFG_CMD_BDI | \
  59                         CFG_CMD_IMI | \
  60                         CFG_CMD_AUTOSCRIPT | \
  61                         CFG_CMD_FPGA | \
  62                         CFG_CMD_MISC | \
  63                         CFG_CMD_LOADS ))
  64
  65 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  66 #include <cmd_confdefs.h>
  67
  68 #define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
  69 #define SECTORSIZE 512
  70
  71 #define ADDR_COLUMN 1
  72 #define ADDR_PAGE 2
  73 #define ADDR_COLUMN_PAGE 3
  74
  75 #define NAND_ChipID_UNKNOWN     0x00
  76 #define NAND_MAX_FLOORS 1
  77 #define NAND_MAX_CHIPS 1
  78
  79 #define AT91_SMART_MEDIA_ALE (1 << 22)  /* our ALE is AD22 */
  80 #define AT91_SMART_MEDIA_CLE (1 << 21)  /* our CLE is AD21 */
  81
  82 #define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
  83 #define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
  84
  85 #define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
  86
  87 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
  88 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
  89 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
  90 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
  91 /* the following are NOP's in our implementation */
  92 #define NAND_CTL_CLRALE(nandptr)
  93 #define NAND_CTL_SETALE(nandptr)
  94 #define NAND_CTL_CLRCLE(nandptr)
  95 #define NAND_CTL_SETCLE(nandptr)
  96
  97 #define CONFIG_NR_DRAM_BANKS 1
  98 #define PHYS_SDRAM 0x20000000
  99 #define PHYS_SDRAM_SIZE 0x2000000  /* 32 megs */
 100
 101 #define CFG_MEMTEST_START PHYS_SDRAM
 102 #define CFG_MEMTEST_END   CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
 103
 104 #define CONFIG_DRIVER_ETHER
 105 #define CONFIG_NET_RETRY_COUNT 20
 106
 107 #define CONFIG_HAS_DATAFLASH    1
 108 #define CFG_SPI_WRITE_TOUT      CFG_HZ
 109 #define CFG_MAX_DATAFLASH_BANKS 2
 110 #define CFG_MAX_DATAFLASH_PAGES 16384
 111 #define CFG_DATAFLASH_LOGIC_ADDR_CS0    0xC0000000      /* Logical adress for CS0 */
 112 #define CFG_DATAFLASH_LOGIC_ADDR_CS3    0xD0000000      /* Logical adress for CS3 */
 113
 114 #define PHYS_FLASH_1 0x10000000
 115 #define PHYS_FLASH_SIZE 0x200000  /* 2 megs main flash */
 116 #define CFG_FLASH_BASE          PHYS_FLASH_1
 117 #define CFG_MAX_FLASH_BANKS 1
 118 #define CFG_MAX_FLASH_SECT 40
 119 #define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase */
 120 #define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write */
 121 #define CFG_ENV_IS_IN_FLASH     1
 122 #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000)  /* 0x10000 */
 123 #define CFG_ENV_SIZE 0x2000  /* 0x8000 */
 124 #define CFG_LOAD_ADDR 0x21000000  /* default load address */
 125
 126 #define CFG_BOOT_SIZE           0x6000 /* 24 KBytes */
 127 #define CFG_U_BOOT_BASE         (PHYS_FLASH_1 + 0x10000)
 128 #define CFG_U_BOOT_SIZE         0x10000 /* 64 KBytes */
 129
 130 #define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
 131
 132 #define CFG_PROMPT "Uboot> " /* Monitor Command Prompt */
 133 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
 134 #define CFG_MAXARGS 16 /* max number of command args */
 135 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 136
 137 #ifndef __ASSEMBLY__
 138 /*-----------------------------------------------------------------------
 139  * Board specific extension for bd_info
 140  *
 141  * This structure is embedded in the global bd_info (bd_t) structure
 142  * and can be used by the board specific code (eg board/...)
 143  */
 144
 145 struct bd_info_ext
 146 {
 147     /* helper variable for board environment handling
 148      *
 149      * env_crc_valid == 0    =>   uninitialised
 150      * env_crc_valid  > 0    =>   environment crc in flash is valid
 151      * env_crc_valid  < 0    =>   environment crc in flash is invalid
 152      */
 153      int        env_crc_valid;
 154 };
 155 #endif
 156
 157 #define CFG_HZ AT91C_MASTER_CLOCK/2  /* AT91C_TC0_CMR is implicitly set to
 158                                         AT91C_TC_TIMER_DIV1_CLOCK */
 159
 160 #define CONFIG_STACKSIZE        (32*1024)       /* regular stack */
 161
 162 #ifdef CONFIG_USE_IRQ
 163 #error CONFIG_USE_IRQ not supported
 164 #endif
 165
 166 #endif