include/configs/at91rm9200ek.h

   1 /*
   2  * Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com>
   3  *
   4  * based on previous work by
   5  *
   6  * Ulf Samuelsson <ulf@atmel.com>
   7  * Rick Bronson <rick@efn.org>
   8  *
   9  * Configuration settings for the AT91RM9200EK board.
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #ifndef __AT91RM9200EK_CONFIG_H__
  15 #define __AT91RM9200EK_CONFIG_H__
  16
  17 #include <linux/sizes.h>
  18
  19 /*
  20  * set some initial configurations depending on configure target
  21  *
  22  * at91rm9200ek_config     -> boot from 0x0 in NOR Flash at CS0
  23  * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel
  24  *                            initialisation was done by some preloader
  25  */
  26 #ifdef CONFIG_RAMBOOT
  27 #define CONFIG_SKIP_LOWLEVEL_INIT
  28 #endif
  29
  30 /*
  31  * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
  32  * AT91C_MAIN_CLOCK is the frequency of PLLA output
  33  * AT91C_MASTER_CLOCK is the peripherial clock
  34  * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
  35  *  set in arch/arm/cpu/arm920t/at91/timer.c)
  36  * CONFIG_SYS_HZ is the tick rate for timer tc0
  37  */
  38 #define AT91C_XTAL_CLOCK                18432000
  39 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768
  40 #define AT91C_MAIN_CLOCK                ((AT91C_XTAL_CLOCK / 4) * 39)
  41 #define AT91C_MASTER_CLOCK              (AT91C_MAIN_CLOCK / 3 )
  42 #define CONFIG_SYS_HZ_CLOCK             (AT91C_MASTER_CLOCK / 2)
  43
  44 /* CPU configuration */
  45 #define CONFIG_AT91RM9200
  46 #define CONFIG_AT91RM9200EK
  47 #define CONFIG_CPUAT91
  48 #define USE_920T_MMU
  49
  50 #include <asm/hardware.h>       /* needed for port definitions */
  51
  52 #define CONFIG_CMDLINE_TAG
  53 #define CONFIG_SETUP_MEMORY_TAGS
  54 #define CONFIG_INITRD_TAG
  55
  56 /*
  57  * Memory Configuration
  58  */
  59 #define CONFIG_NR_DRAM_BANKS            1
  60 #define CONFIG_SYS_SDRAM_BASE           0x20000000
  61 #define CONFIG_SYS_SDRAM_SIZE           SZ_32M
  62
  63 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
  64 #define CONFIG_SYS_MEMTEST_END          \
  65                 (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)
  66
  67 /*
  68  * LowLevel Init
  69  */
  70 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  71 #define CONFIG_SYS_USE_MAIN_OSCILLATOR
  72 /* flash */
  73 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
  74 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
  75
  76 /* clocks */
  77 #define CONFIG_SYS_PLLAR_VAL    0x20263E04 /* 179.712000 MHz for PCK */
  78 #define CONFIG_SYS_PLLBR_VAL    0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
  79 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
  80 #define CONFIG_SYS_MCKR_VAL     0x00000202
  81
  82 /* sdram */
  83 #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
  84 #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
  85 #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
  86 #define CONFIG_SYS_EBI_CSA_VAL  0x00000002 /* CS1=CONFIG_SYS_SDRAM */
  87 #define CONFIG_SYS_SDRC_CR_VAL  0x2188c155 /* set up the CONFIG_SYS_SDRAM */
  88 #define CONFIG_SYS_SDRAM        CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
  89 #define CONFIG_SYS_SDRAM1       (CONFIG_SYS_SDRAM_BASE+0x80)
  90 #define CONFIG_SYS_SDRAM_VAL    0x00000000 /* value written to CONFIG_SYS_SDRAM */
  91 #define CONFIG_SYS_SDRC_MR_VAL  0x00000002 /* Precharge All */
  92 #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
  93 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
  94 #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
  95 #define CONFIG_SYS_SDRC_TR_VAL  0x000002E0 /* Write refresh rate */
  96 #endif  /* CONFIG_SKIP_LOWLEVEL_INIT */
  97
  98 /*
  99  * Hardware drivers
 100  */
 101 /*
 102  * Choose a USART for serial console
 103  * CONFIG_DBGU is DBGU unit on J10
 104  * CONFIG_USART1 is USART1 on J14
 105  */
 106 #define CONFIG_ATMEL_USART
 107 #define CONFIG_USART_BASE       ATMEL_BASE_DBGU
 108 #define CONFIG_USART_ID         0/* ignored in arm */
 109
 110 /*
 111  * Command line configuration.
 112  */
 113
 114 /*
 115  * Network Driver Setting
 116  */
 117 #define CONFIG_DRIVER_AT91EMAC
 118 #define CONFIG_SYS_RX_ETH_BUFFER        16
 119 #define CONFIG_RMII
 120 #define CONFIG_MII
 121
 122 /*
 123  * NOR Flash
 124  */
 125 #define CONFIG_FLASH_CFI_DRIVER
 126 #define CONFIG_SYS_FLASH_CFI
 127 #define CONFIG_SYS_FLASH_BASE           0x10000000
 128 #define PHYS_FLASH_1                    CONFIG_SYS_FLASH_BASE
 129 #define PHYS_FLASH_SIZE                 SZ_8M
 130 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 131 #define CONFIG_SYS_MAX_FLASH_SECT       256
 132 #define CONFIG_SYS_FLASH_PROTECTION
 133
 134 /*
 135  * USB Config
 136  */
 137 #define CONFIG_USB_ATMEL                        1
 138 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 139 #define CONFIG_USB_OHCI_NEW                     1
 140
 141 #define CONFIG_SYS_USB_OHCI_CPU_INIT            1
 142 #define CONFIG_SYS_USB_OHCI_REGS_BASE           ATMEL_USB_HOST_BASE
 143 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91rm9200"
 144 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 145
 146 /*
 147  * Environment Settings
 148  */
 149
 150 /*
 151  * after u-boot.bin
 152  */
 153 #define CONFIG_ENV_ADDR                 \
 154                 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 155 #define CONFIG_ENV_SIZE                 SZ_64K /* sectors are 64K here */
 156 /* The following #defines are needed to get flash environment right */
 157 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 158 #define CONFIG_SYS_MONITOR_LEN          SZ_256K
 159
 160 /*
 161  * Boot option
 162  */
 163
 164 /* default load address */
 165 #define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_SDRAM_BASE + SZ_16M
 166 #define CONFIG_ENV_OVERWRITE
 167
 168 /*
 169  * Shell Settings
 170  */
 171 #define CONFIG_CMDLINE_EDITING
 172 #define CONFIG_SYS_LONGHELP
 173 #define CONFIG_AUTO_COMPLETE
 174
 175 /*
 176  * Size of malloc() pool
 177  */
 178 #define CONFIG_SYS_MALLOC_LEN           ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
 179                                              SZ_4K)
 180
 181 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + SZ_4K \
 182                                         - GENERATED_GBL_DATA_SIZE)
 183
 184 #endif /* __AT91RM9200EK_CONFIG_H__ */