include/configs/at91rm9200ek.h

   1 /*
   2  * Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com>
   3  *
   4  * based on previous work by
   5  *
   6  * Ulf Samuelsson <ulf@atmel.com>
   7  * Rick Bronson <rick@efn.org>
   8  *
   9  * Configuration settings for the AT91RM9200EK board.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #ifndef __AT91RM9200EK_CONFIG_H__
  31 #define __AT91RM9200EK_CONFIG_H__
  32
  33 #include <asm/sizes.h>
  34
  35 /*
  36  * set some initial configurations depending on configure target
  37  *
  38  * at91rm9200ek_config     -> boot from 0x0 in NOR Flash at CS0
  39  * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel
  40  *                            initialisation was done by some preloader
  41  */
  42 #ifdef CONFIG_RAMBOOT
  43 #define CONFIG_SKIP_LOWLEVEL_INIT
  44 #define CONFIG_SYS_TEXT_BASE 0x20100000
  45 #else
  46 #define CONFIG_SYS_TEXT_BASE 0x10000000
  47 #endif
  48
  49 /*
  50  * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
  51  * AT91C_MAIN_CLOCK is the frequency of PLLA output
  52  * AT91C_MASTER_CLOCK is the peripherial clock
  53  * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
  54  *  set in arch/arm/cpu/arm920t/at91/timer.c)
  55  * CONFIG_SYS_HZ is the tick rate for timer tc0
  56  */
  57 #define AT91C_XTAL_CLOCK                18432000
  58 #define AT91C_MAIN_CLOCK                ((AT91C_XTAL_CLOCK / 4) * 39)
  59 #define AT91C_MASTER_CLOCK              (AT91C_MAIN_CLOCK / 3 )
  60 #define CONFIG_SYS_HZ_CLOCK             (AT91C_MASTER_CLOCK / 2)
  61 #define CONFIG_SYS_HZ                   1000
  62
  63 /* CPU configuration */
  64 #define CONFIG_AT91RM9200
  65 #define CONFIG_AT91RM9200EK
  66 #define CONFIG_CPUAT91
  67 #define USE_920T_MMU
  68
  69 #define CONFIG_CMDLINE_TAG
  70 #define CONFIG_SETUP_MEMORY_TAGS
  71 #define CONFIG_INITRD_TAG
  72
  73 /*
  74  * Memory Configuration
  75  */
  76 #define CONFIG_NR_DRAM_BANKS            1
  77 #define CONFIG_SYS_SDRAM_BASE           0x20000000
  78 #define CONFIG_SYS_SDRAM_SIZE           SZ_32M
  79
  80 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
  81 #define CONFIG_SYS_MEMTEST_END          \
  82                 (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)
  83
  84 /*
  85  * LowLevel Init
  86  */
  87 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  88 #define CONFIG_SYS_USE_MAIN_OSCILLATOR
  89 /* flash */
  90 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
  91 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
  92
  93 /* clocks */
  94 #define CONFIG_SYS_PLLAR_VAL    0x20263E04 /* 179.712000 MHz for PCK */
  95 #define CONFIG_SYS_PLLBR_VAL    0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
  96 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
  97 #define CONFIG_SYS_MCKR_VAL     0x00000202
  98
  99 /* sdram */
 100 #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
 101 #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
 102 #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
 103 #define CONFIG_SYS_EBI_CSA_VAL  0x00000002 /* CS1=CONFIG_SYS_SDRAM */
 104 #define CONFIG_SYS_SDRC_CR_VAL  0x2188c155 /* set up the CONFIG_SYS_SDRAM */
 105 #define CONFIG_SYS_SDRAM        CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
 106 #define CONFIG_SYS_SDRAM1       (CONFIG_SYS_SDRAM_BASE+0x80)
 107 #define CONFIG_SYS_SDRAM_VAL    0x00000000 /* value written to CONFIG_SYS_SDRAM */
 108 #define CONFIG_SYS_SDRC_MR_VAL  0x00000002 /* Precharge All */
 109 #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
 110 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
 111 #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
 112 #define CONFIG_SYS_SDRC_TR_VAL  0x000002E0 /* Write refresh rate */
 113 #endif  /* CONFIG_SKIP_LOWLEVEL_INIT */
 114
 115 /*
 116  * Hardware drivers
 117  */
 118 /*
 119  * Choose a USART for serial console
 120  * CONFIG_DBGU is DBGU unit on J10
 121  * CONFIG_USART1 is USART1 on J14
 122  */
 123 #define CONFIG_AT91RM9200_USART
 124 #define CONFIG_DBGU
 125
 126 #define CONFIG_SYS_BAUDRATE_TABLE       {115200 , 19200, 38400, 57600, 9600 }
 127 #define CONFIG_BAUDRATE                 115200
 128
 129 /*
 130  * Command line configuration.
 131  */
 132 #include <config_cmd_default.h>
 133
 134 #define CONFIG_CMD_DHCP
 135 #define CONFIG_CMD_FAT
 136 #define CONFIG_CMD_MII
 137 #define CONFIG_CMD_PING
 138 #define CONFIG_CMD_USB
 139 #undef CONFIG_CMD_FPGA
 140
 141 /*
 142  * Network Driver Setting
 143  */
 144 #define CONFIG_NET_MULTI
 145 #define CONFIG_DRIVER_AT91EMAC
 146 #define CONFIG_SYS_RX_ETH_BUFFER        16
 147 #define CONFIG_RMII
 148 #define CONFIG_MII
 149
 150 /*
 151  * NOR Flash
 152  */
 153 #define CONFIG_FLASH_CFI_DRIVER
 154 #define CONFIG_SYS_FLASH_CFI
 155 #define CONFIG_SYS_FLASH_BASE           0x10000000
 156 #define PHYS_FLASH_1                    CONFIG_SYS_FLASH_BASE
 157 #define PHYS_FLASH_SIZE                 SZ_8M
 158 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 159 #define CONFIG_SYS_MAX_FLASH_SECT       256
 160 #define CONFIG_SYS_FLASH_PROTECTION
 161
 162 /*
 163  * USB Config
 164  */
 165 #define CONFIG_USB_ATMEL                        1
 166 #define CONFIG_USB_OHCI_NEW                     1
 167 #define CONFIG_USB_KEYBOARD                     1
 168 #define CONFIG_USB_STORAGE                      1
 169 #define CONFIG_DOS_PARTITION                    1
 170
 171 #define CONFIG_SYS_USB_OHCI_CPU_INIT            1
 172 #define CONFIG_SYS_USB_OHCI_REGS_BASE           ATMEL_USB_HOST_BASE
 173 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91rm9200"
 174 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 175
 176 /*
 177  * Environment Settings
 178  */
 179 #define CONFIG_ENV_IS_IN_FLASH
 180
 181 /*
 182  * after u-boot.bin
 183  */
 184 #define CONFIG_ENV_ADDR                 \
 185                 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 186 #define CONFIG_ENV_SIZE                 SZ_64K /* sectors are 64K here */
 187 /* The following #defines are needed to get flash environment right */
 188 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 189 #define CONFIG_SYS_MONITOR_LEN          SZ_256K
 190
 191 /*
 192  * Boot option
 193  */
 194 #define CONFIG_BOOTDELAY                3
 195
 196 /* default load address */
 197 #define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_SDRAM_BASE + SZ_16M
 198 #define CONFIG_ENV_OVERWRITE
 199
 200 /*
 201  * Shell Settings
 202  */
 203 #define CONFIG_CMDLINE_EDITING
 204 #define CONFIG_SYS_LONGHELP
 205 #define CONFIG_AUTO_COMPLETE
 206 #define CONFIG_SYS_HUSH_PARSER
 207 #define CONFIG_SYS_PROMPT               "U-Boot> "
 208 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 209 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 210 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 211 /* Print Buffer Size */
 212 #define CONFIG_SYS_PBSIZE               \
 213                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 214
 215 /*
 216  * Size of malloc() pool
 217  */
 218 #define CONFIG_SYS_MALLOC_LEN           ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
 219                                              SZ_4K)
 220
 221 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + SZ_4K \
 222                                         - GENERATED_GBL_DATA_SIZE)
 223
 224 #define CONFIG_STACKSIZE                SZ_32K  /* regular stack */
 225 #define CONFIG_STACKSIZE_IRQ            SZ_4K   /* Unsure if to big or to small*/
 226 #define CONFIG_STACKSIZE_FIQ            SZ_4K   /* Unsure if to big or to small*/
 227 #endif /* __AT91RM9200EK_CONFIG_H__ */