include/configs/at91sam9263ek.h

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * Configuation settings for the AT91SAM9263EK board.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /* ARM asynchronous clock */
  31 #define CONFIG_SYS_AT91_MAIN_CLOCK      16367660        /* 16.367 MHz crystal */
  32 #define CONFIG_SYS_HZ           1000
  33
  34 #define CONFIG_ARM926EJS        1       /* This is an ARM926EJS Core    */
  35 #define CONFIG_AT91SAM9263      1       /* It's an Atmel AT91SAM9263 SoC*/
  36 #define CONFIG_AT91SAM9263EK    1       /* on an AT91SAM9263EK Board    */
  37 #define CONFIG_ARCH_CPU_INIT
  38 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff  */
  39
  40 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs      */
  41 #define CONFIG_SETUP_MEMORY_TAGS 1
  42 #define CONFIG_INITRD_TAG       1
  43
  44 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
  45 #define CONFIG_SKIP_LOWLEVEL_INIT
  46 #define CONFIG_SKIP_RELOCATE_UBOOT
  47 #endif
  48
  49 /*
  50  * Hardware drivers
  51  */
  52 #define CONFIG_AT91_GPIO        1
  53 #define CONFIG_ATMEL_USART      1
  54 #undef CONFIG_USART0
  55 #undef CONFIG_USART1
  56 #undef CONFIG_USART2
  57 #define CONFIG_USART3           1       /* USART 3 is DBGU */
  58
  59 /* LCD */
  60 #define CONFIG_LCD                      1
  61 #define LCD_BPP                         LCD_COLOR8
  62 #define CONFIG_LCD_LOGO                 1
  63 #undef LCD_TEST_PATTERN
  64 #define CONFIG_LCD_INFO                 1
  65 #define CONFIG_LCD_INFO_BELOW_LOGO      1
  66 #define CONFIG_SYS_WHITE_ON_BLACK               1
  67 #define CONFIG_ATMEL_LCD                1
  68 #define CONFIG_ATMEL_LCD_BGR555         1
  69 #define CONFIG_SYS_CONSOLE_IS_IN_ENV            1
  70
  71 /* LED */
  72 #define CONFIG_AT91_LED
  73 #define CONFIG_RED_LED          AT91_PIO_PORTB, 7       /* the power led */
  74 #define CONFIG_GREEN_LED        AT91_PIO_PORTB, 8       /* the user1 led */
  75 #define CONFIG_YELLOW_LED       AT91_PIO_PORTC, 29      /* the user2 led */
  76
  77 #define CONFIG_BOOTDELAY        3
  78
  79 /*
  80  * BOOTP options
  81  */
  82 #define CONFIG_BOOTP_BOOTFILESIZE       1
  83 #define CONFIG_BOOTP_BOOTPATH           1
  84 #define CONFIG_BOOTP_GATEWAY            1
  85 #define CONFIG_BOOTP_HOSTNAME           1
  86
  87 /*
  88  * Command line configuration.
  89  */
  90 #include <config_cmd_default.h>
  91 #undef CONFIG_CMD_BDI
  92 #undef CONFIG_CMD_FPGA
  93 #undef CONFIG_CMD_IMI
  94 #undef CONFIG_CMD_IMLS
  95 #undef CONFIG_CMD_LOADS
  96 #undef CONFIG_CMD_SOURCE
  97
  98 #define CONFIG_CMD_PING         1
  99 #define CONFIG_CMD_DHCP         1
 100 #define CONFIG_CMD_NAND         1
 101 #define CONFIG_CMD_USB          1
 102
 103 /* SDRAM */
 104 #define CONFIG_NR_DRAM_BANKS            1
 105 #define PHYS_SDRAM                      0x20000000
 106 #define PHYS_SDRAM_SIZE                 0x04000000      /* 64 megs */
 107
 108 /* DataFlash */
 109 #define CONFIG_ATMEL_DATAFLASH_SPI
 110 #define CONFIG_HAS_DATAFLASH            1
 111 #define CONFIG_SYS_SPI_WRITE_TOUT               (5*CONFIG_SYS_HZ)
 112 #define CONFIG_SYS_MAX_DATAFLASH_BANKS          1
 113 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0     0xC0000000      /* CS0 */
 114 #define AT91_SPI_CLK                    15000000
 115 #define DATAFLASH_TCSS                  (0x1a << 16)
 116 #define DATAFLASH_TCHS                  (0x1 << 24)
 117
 118 /* NOR flash, if populated */
 119 #ifdef CONFIG_SYS_USE_NORFLASH
 120 #define CONFIG_SYS_FLASH_CFI                    1
 121 #define CONFIG_FLASH_CFI_DRIVER                 1
 122 #define PHYS_FLASH_1                            0x10000000
 123 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
 124 #define CONFIG_SYS_MAX_FLASH_SECT               256
 125 #define CONFIG_SYS_MAX_FLASH_BANKS              1
 126
 127 #define CONFIG_SYS_MONITOR_SEC  1:0-3
 128 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 129 #define CONFIG_SYS_MONITOR_LEN  (256 << 10)
 130 #define CONFIG_ENV_IS_IN_FLASH  1
 131 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x007FE000)
 132 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
 133
 134 /* Address and size of Primary Environment Sector */
 135 #define CONFIG_ENV_SIZE         0x2000
 136
 137 #define xstr(s)   str(s)
 138 #define str(s)  #s
 139
 140 #define CONFIG_EXTRA_ENV_SETTINGS       \
 141         "monitor_base=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
 142         "update=" \
 143                 "protect off ${monitor_base} +${filesize};" \
 144                 "erase ${monitor_base} +${filesize};" \
 145                 "cp.b ${load_addr} ${monitor_base} ${filesize};" \
 146                 "protect on ${monitor_base} +${filesize}\0"
 147
 148 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 149 #define MASTER_PLL_MUL          171
 150 #define MASTER_PLL_DIV          14
 151 #define MASTER_PLL_OUT          3
 152
 153 /* clocks */
 154 #define CONFIG_SYS_MOR_VAL                                              \
 155                 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
 156 #define CONFIG_SYS_PLLAR_VAL                                    \
 157         (AT91_PMC_PLLAR_29 |                                    \
 158         AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |                    \
 159         AT91_PMC_PLLXR_PLLCOUNT(63) |                           \
 160         AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) |                \
 161         AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
 162
 163 /* PCK/2 = MCK Master Clock from PLLA */
 164 #define CONFIG_SYS_MCKR1_VAL            \
 165         (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |        \
 166          AT91_PMC_MCKR_MDIV_2)
 167
 168 /* PCK/2 = MCK Master Clock from PLLA */
 169 #define CONFIG_SYS_MCKR2_VAL            \
 170         (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 |        \
 171         AT91_PMC_MCKR_MDIV_2)
 172
 173 /* define PDC[31:16] as DATA[31:16] */
 174 #define CONFIG_SYS_PIOD_PDR_VAL1        0xFFFF0000
 175 /* no pull-up for D[31:16] */
 176 #define CONFIG_SYS_PIOD_PPUDR_VAL       0xFFFF0000
 177 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
 178 #define CONFIG_SYS_MATRIX_EBICSA_VAL                                    \
 179         (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |       \
 180          AT91_MATRIX_CSA_EBI_CS1A)
 181
 182 /* SDRAM */
 183 /* SDRAMC_MR Mode register */
 184 #define CONFIG_SYS_SDRC_MR_VAL1         0
 185 /* SDRAMC_TR - Refresh Timer register */
 186 #define CONFIG_SYS_SDRC_TR_VAL1         0x13C
 187 /* SDRAMC_CR - Configuration register*/
 188 #define CONFIG_SYS_SDRC_CR_VAL                                                  \
 189                 (AT91_SDRAMC_NC_9 |                                             \
 190                  AT91_SDRAMC_NR_13 |                                            \
 191                  AT91_SDRAMC_NB_4 |                                             \
 192                  AT91_SDRAMC_CAS_3 |                                            \
 193                  AT91_SDRAMC_DBW_32 |                                           \
 194                  (1 <<  8) |            /* Write Recovery Delay */              \
 195                  (7 << 12) |            /* Row Cycle Delay */                   \
 196                  (2 << 16) |            /* Row Precharge Delay */               \
 197                  (2 << 20) |            /* Row to Column Delay */               \
 198                  (5 << 24) |            /* Active to Precharge Delay */         \
 199                  (1 << 28))             /* Exit Self Refresh to Active Delay */
 200
 201 /* Memory Device Register -> SDRAM */
 202 #define CONFIG_SYS_SDRC_MDR_VAL         AT91_SDRAMC_MD_SDRAM
 203 #define CONFIG_SYS_SDRC_MR_VAL2         AT91_SDRAMC_MODE_PRECHARGE
 204 #define CONFIG_SYS_SDRAM_VAL1           0               /* SDRAM_BASE */
 205 #define CONFIG_SYS_SDRC_MR_VAL3         AT91_SDRAMC_MODE_REFRESH
 206 #define CONFIG_SYS_SDRAM_VAL2           0               /* SDRAM_BASE */
 207 #define CONFIG_SYS_SDRAM_VAL3           0               /* SDRAM_BASE */
 208 #define CONFIG_SYS_SDRAM_VAL4           0               /* SDRAM_BASE */
 209 #define CONFIG_SYS_SDRAM_VAL5           0               /* SDRAM_BASE */
 210 #define CONFIG_SYS_SDRAM_VAL6           0               /* SDRAM_BASE */
 211 #define CONFIG_SYS_SDRAM_VAL7           0               /* SDRAM_BASE */
 212 #define CONFIG_SYS_SDRAM_VAL8           0               /* SDRAM_BASE */
 213 #define CONFIG_SYS_SDRAM_VAL9           0               /* SDRAM_BASE */
 214 #define CONFIG_SYS_SDRC_MR_VAL4         AT91_SDRAMC_MODE_LMR
 215 #define CONFIG_SYS_SDRAM_VAL10          0               /* SDRAM_BASE */
 216 #define CONFIG_SYS_SDRC_MR_VAL5         AT91_SDRAMC_MODE_NORMAL
 217 #define CONFIG_SYS_SDRAM_VAL11          0               /* SDRAM_BASE */
 218 #define CONFIG_SYS_SDRC_TR_VAL2         1200            /* SDRAM_TR */
 219 #define CONFIG_SYS_SDRAM_VAL12          0               /* SDRAM_BASE */
 220
 221 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
 222 #define CONFIG_SYS_SMC0_SETUP0_VAL                              \
 223         (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |   \
 224          AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
 225 #define CONFIG_SYS_SMC0_PULSE0_VAL                              \
 226         (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |   \
 227          AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
 228 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
 229         (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
 230 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
 231         (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |          \
 232          AT91_SMC_MODE_DBW_16 |                                 \
 233          AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
 234
 235 /* user reset enable */
 236 #define CONFIG_SYS_RSTC_RMR_VAL                 \
 237                 (AT91_RSTC_KEY |                \
 238                 AT91_RSTC_MR_URSTEN |           \
 239                 AT91_RSTC_MR_ERSTL(15))
 240
 241 /* Disable Watchdog */
 242 #define CONFIG_SYS_WDTC_WDMR_VAL                                \
 243                 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
 244                  AT91_WDT_MR_WDV(0xfff) |                       \
 245                  AT91_WDT_MR_WDDIS |                            \
 246                  AT91_WDT_MR_WDD(0xfff))
 247
 248 #endif
 249
 250 #else
 251 #define CONFIG_SYS_NO_FLASH                     1
 252 #endif
 253
 254 /* NAND flash */
 255 #ifdef CONFIG_CMD_NAND
 256 #define CONFIG_NAND_ATMEL
 257 #define CONFIG_SYS_MAX_NAND_DEVICE              1
 258 #define CONFIG_SYS_NAND_BASE                    0x40000000
 259 #define CONFIG_SYS_NAND_DBW_8                   1
 260 /* our ALE is AD21 */
 261 #define CONFIG_SYS_NAND_MASK_ALE                (1 << 21)
 262 /* our CLE is AD22 */
 263 #define CONFIG_SYS_NAND_MASK_CLE                (1 << 22)
 264 #define CONFIG_SYS_NAND_ENABLE_PIN      AT91_PIO_PORTD, 15
 265 #define CONFIG_SYS_NAND_READY_PIN       AT91_PIO_PORTA, 22
 266 /*
 267 #define CONFIG_SYS_NAND_ENABLE_PIN  AT91_PIN_PD15
 268 #define CONFIG_SYS_NAND_READY_PIN  AT91_PIN_PA22
 269 */
 270
 271
 272 #define CONFIG_SYS_64BIT_VSPRINTF               /* needed for nand_util.c */
 273 #endif
 274
 275 /* Ethernet */
 276 #define CONFIG_MACB                     1
 277 #define CONFIG_RMII                     1
 278 #define CONFIG_NET_MULTI                1
 279 #define CONFIG_NET_RETRY_COUNT          20
 280 #define CONFIG_RESET_PHY_R              1
 281
 282 /* USB */
 283 #define CONFIG_USB_ATMEL
 284 #define CONFIG_USB_OHCI_NEW             1
 285 #define CONFIG_DOS_PARTITION            1
 286 #define CONFIG_SYS_USB_OHCI_CPU_INIT            1
 287 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00a00000      /* AT91SAM9263_UHP_BASE */
 288 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9263"
 289 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 290 #define CONFIG_USB_STORAGE              1
 291 #define CONFIG_CMD_FAT                  1
 292
 293 #define CONFIG_SYS_LOAD_ADDR                    0x22000000      /* load address */
 294
 295 #define CONFIG_SYS_MEMTEST_START                PHYS_SDRAM
 296 #define CONFIG_SYS_MEMTEST_END                  0x23e00000
 297
 298 #ifdef CONFIG_SYS_USE_DATAFLASH
 299
 300 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 301 #define CONFIG_ENV_IS_IN_DATAFLASH      1
 302 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
 303 #define CONFIG_ENV_OFFSET               0x4200
 304 #define CONFIG_ENV_ADDR         (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 305 #define CONFIG_ENV_SIZE         0x4200
 306 #define CONFIG_BOOTCOMMAND      "cp.b 0xC0042000 0x22000000 0x210000; bootm"
 307 #define CONFIG_BOOTARGS         "console=ttyS0,115200 " \
 308                                 "root=/dev/mtdblock0 " \
 309                                 "mtdparts=atmel_nand:-(root) "\
 310                                 "rw rootfstype=jffs2"
 311
 312 #elif CONFIG_SYS_USE_NANDFLASH
 313
 314 /* bootstrap + u-boot + env + linux in nandflash */
 315 #define CONFIG_ENV_IS_IN_NAND   1
 316 #define CONFIG_ENV_OFFSET               0x60000
 317 #define CONFIG_ENV_OFFSET_REDUND        0x80000
 318 #define CONFIG_ENV_SIZE         0x20000         /* 1 sector = 128 kB */
 319 #define CONFIG_BOOTCOMMAND      "nand read 0x22000000 0xA0000 0x200000; bootm"
 320 #define CONFIG_BOOTARGS         "console=ttyS0,115200 " \
 321                                 "root=/dev/mtdblock5 " \
 322                                 "mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
 323                                 "rw rootfstype=jffs2"
 324
 325 #endif
 326
 327 #define CONFIG_BAUDRATE         115200
 328 #define CONFIG_SYS_BAUDRATE_TABLE       {115200 , 19200, 38400, 57600, 9600 }
 329
 330 #define CONFIG_SYS_PROMPT               "U-Boot> "
 331 #define CONFIG_SYS_CBSIZE               256
 332 #define CONFIG_SYS_MAXARGS              16
 333 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 334 #define CONFIG_SYS_LONGHELP             1
 335 #define CONFIG_CMDLINE_EDITING  1
 336 #define CONFIG_AUTO_COMPLETE
 337 #define CONFIG_SYS_HUSH_PARSER
 338 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 339
 340 /*
 341  * Size of malloc() pool
 342  */
 343 #define CONFIG_SYS_MALLOC_LEN           ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
 344 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* 128 bytes for initial data */
 345
 346 #define CONFIG_STACKSIZE        (32*1024)       /* regular stack */
 347
 348 #ifdef CONFIG_USE_IRQ
 349 #error CONFIG_USE_IRQ not supported
 350 #endif
 351
 352 #endif