include/configs/atc.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU               */
  37 #define CONFIG_ATC              1       /* ...on a ATC board    */
  38 #define CONFIG_CPM2             1       /* Has a CPM2 */
  39
  40 #define CONFIG_SYS_TEXT_BASE    0xFF000000
  41
  42 /*
  43  * select serial console configuration
  44  *
  45  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  46  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  47  * for SCC).
  48  *
  49  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  50  * defined elsewhere (for example, on the cogent platform, there are serial
  51  * ports on the motherboard which are used for the serial console - see
  52  * cogent/cma101/serial.[ch]).
  53  */
  54 #define  CONFIG_CONS_ON_SMC             /* define if console on SMC */
  55 #undef CONFIG_CONS_ON_SCC               /* define if console on SCC */
  56 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  57 #define CONFIG_CONS_INDEX       2       /* which serial channel for console */
  58
  59 #define CONFIG_BAUDRATE         115200
  60
  61 /*
  62  * select ethernet configuration
  63  *
  64  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  65  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  66  * for FCC)
  67  *
  68  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  69  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  70  */
  71 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
  72 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  73 #define CONFIG_ETHER_ON_FCC
  74
  75 #define CONFIG_ETHER_ON_FCC2
  76
  77 /*
  78  * - Rx-CLK is CLK13
  79  * - Tx-CLK is CLK14
  80  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  81  * - Enable Full Duplex in FSMR
  82  */
  83 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
  84 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
  85 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  86 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  87
  88 #define CONFIG_ETHER_ON_FCC3
  89
  90 /*
  91  * - Rx-CLK is CLK15
  92  * - Tx-CLK is CLK16
  93  * - RAM for BD/Buffers is on the local Bus (see 28-13)
  94  * - Enable Half Duplex in FSMR
  95  */
  96 # define CONFIG_SYS_CMXFCR_MASK3        (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
  97 # define CONFIG_SYS_CMXFCR_VALUE3       (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
  98
  99 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 100 #define CONFIG_8260_CLKIN       64000000        /* in Hz */
 101
 102 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 103
 104 #undef  CONFIG_CLOCKS_IN_MHZ            /* clocks passsed to Linux in Hz */
 105
 106 #define CONFIG_PREBOOT                                                  \
 107         "echo;"                                                         \
 108         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;"\
 109         "echo"
 110
 111 #undef  CONFIG_BOOTARGS
 112 #define CONFIG_BOOTCOMMAND                                              \
 113         "bootp;"                                                        \
 114         "setenv bootargs root=/dev/nfs rw "                             \
 115         "nfsroot=${serverip}:${rootpath} "                              \
 116         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
 117         "bootm"
 118
 119 /*-----------------------------------------------------------------------
 120  * Miscellaneous configuration options
 121  */
 122
 123 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 124 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 125
 126
 127 /*
 128  * BOOTP options
 129  */
 130 #define CONFIG_BOOTP_SUBNETMASK
 131 #define CONFIG_BOOTP_GATEWAY
 132 #define CONFIG_BOOTP_HOSTNAME
 133 #define CONFIG_BOOTP_BOOTPATH
 134 #define CONFIG_BOOTP_BOOTFILESIZE
 135
 136
 137 /*
 138  * Command line configuration.
 139  */
 140 #include <config_cmd_default.h>
 141
 142 #define CONFIG_CMD_EEPROM
 143 #define CONFIG_CMD_PCI
 144 #define CONFIG_CMD_PCMCIA
 145 #define CONFIG_CMD_DATE
 146 #define CONFIG_CMD_IDE
 147
 148
 149 #define CONFIG_DOS_PARTITION
 150
 151 /*
 152  * Miscellaneous configurable options
 153  */
 154 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 155 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 156 #if defined(CONFIG_CMD_KGDB)
 157 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 158 #else
 159 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 160 #endif
 161 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 162 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 163 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 164
 165 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 166 #define CONFIG_SYS_MEMTEST_END  0x0C00000       /* 4 ... 12 MB in DRAM  */
 167
 168 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 169
 170 #define CONFIG_SYS_PIO_MODE             0       /* IDE interface in PIO Mode 0  */
 171
 172 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 173
 174 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100     /* "bad" address                */
 175
 176 #define CONFIG_SYS_ALLOC_DPRAM
 177
 178 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 179
 180 #define CONFIG_SPI
 181
 182 #define CONFIG_RTC_DS12887
 183
 184 #define RTC_BASE_ADDR           0xF5000000
 185 #define RTC_PORT_ADDR           RTC_BASE_ADDR + 0x800
 186 #define RTC_PORT_DATA           RTC_BASE_ADDR + 0x808
 187
 188 #define CONFIG_MISC_INIT_R
 189
 190 /*
 191  * For booting Linux, the board info and command line data
 192  * have to be in the first 8 MB of memory, since this is
 193  * the maximum mapped by the Linux kernel during initialization.
 194  */
 195 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 196
 197 /*-----------------------------------------------------------------------
 198  * Flash configuration
 199  */
 200
 201 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 202 #define CONFIG_SYS_FLASH_SIZE           0x00800000
 203
 204 /*-----------------------------------------------------------------------
 205  * FLASH organization
 206  */
 207 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 208 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 209
 210 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 211 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 212
 213 #define CONFIG_FLASH_16BIT
 214
 215 /*-----------------------------------------------------------------------
 216  * Hard Reset Configuration Words
 217  *
 218  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 219  * defines for the various registers affected by the HRCW e.g. changing
 220  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 221  */
 222 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
 223                                  HRCW_BPS10 |\
 224                                  HRCW_APPC10)
 225
 226 /* no slaves so just fill with zeros */
 227 #define CONFIG_SYS_HRCW_SLAVE1          0
 228 #define CONFIG_SYS_HRCW_SLAVE2          0
 229 #define CONFIG_SYS_HRCW_SLAVE3          0
 230 #define CONFIG_SYS_HRCW_SLAVE4          0
 231 #define CONFIG_SYS_HRCW_SLAVE5          0
 232 #define CONFIG_SYS_HRCW_SLAVE6          0
 233 #define CONFIG_SYS_HRCW_SLAVE7          0
 234
 235 /*-----------------------------------------------------------------------
 236  * Internal Memory Mapped Register
 237  */
 238 #define CONFIG_SYS_IMMR         0xF0000000
 239
 240 /*-----------------------------------------------------------------------
 241  * Definitions for initial stack pointer and data area (in DPRAM)
 242  */
 243 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 244 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM    */
 245 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 246 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 247
 248 /*-----------------------------------------------------------------------
 249  * Start addresses for the final memory configuration
 250  * (Set up by the startup code)
 251  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 252  *
 253  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
 254  */
 255 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 256 #define CONFIG_SYS_SDRAM_MAX_SIZE       0x08000000      /* max. 128 MB          */
 257 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 258 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor */
 259 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 260
 261 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 262 # define CONFIG_SYS_RAMBOOT
 263 #endif
 264
 265 #define CONFIG_PCI
 266 #define CONFIG_PCI_PNP
 267 #define CONFIG_SYS_PCI_MSTR_IO_BUS      0x00000000      /* PCI base   */
 268
 269 #if 1
 270 /* environment is in Flash */
 271 #define CONFIG_ENV_IS_IN_FLASH  1
 272 # define CONFIG_ENV_ADDR                (CONFIG_SYS_FLASH_BASE+0x30000)
 273 # define CONFIG_ENV_SIZE                0x10000
 274 # define CONFIG_ENV_SECT_SIZE   0x10000
 275 #else
 276 #define CONFIG_ENV_IS_IN_EEPROM 1
 277 #define CONFIG_ENV_OFFSET               0
 278 #define CONFIG_ENV_SIZE         2048
 279 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4       /* 16-byte page size    */
 280 #endif
 281
 282 /*-----------------------------------------------------------------------
 283  * Cache Configuration
 284  */
 285 #define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 286 #if defined(CONFIG_CMD_KGDB)
 287 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 288 #endif
 289
 290 /*-----------------------------------------------------------------------
 291  * HIDx - Hardware Implementation-dependent Registers                    2-11
 292  *-----------------------------------------------------------------------
 293  * HID0 also contains cache control - initially enable both caches and
 294  * invalidate contents, then the final state leaves only the instruction
 295  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 296  * but Soft reset does not.
 297  *
 298  * HID1 has only read-only information - nothing to set.
 299  */
 300 #define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
 301                          HID0_DCI|HID0_IFEM|HID0_ABE)
 302 #define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 303 #define CONFIG_SYS_HID2        0
 304
 305 /*-----------------------------------------------------------------------
 306  * RMR - Reset Mode Register                                     5-5
 307  *-----------------------------------------------------------------------
 308  * turn on Checkstop Reset Enable
 309  */
 310 #define CONFIG_SYS_RMR         RMR_CSRE
 311
 312 /*-----------------------------------------------------------------------
 313  * BCR - Bus Configuration                                       4-25
 314  *-----------------------------------------------------------------------
 315  */
 316 #define BCR_APD01       0x10000000
 317 #define CONFIG_SYS_BCR          (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 318
 319 /*-----------------------------------------------------------------------
 320  * SIUMCR - SIU Module Configuration                             4-31
 321  *-----------------------------------------------------------------------
 322  */
 323 #define CONFIG_SYS_SIUMCR      (SIUMCR_BBD|SIUMCR_APPC10|\
 324                          SIUMCR_CS10PC00|SIUMCR_BCTLC10)
 325
 326 /*-----------------------------------------------------------------------
 327  * SYPCR - System Protection Control                             4-35
 328  * SYPCR can only be written once after reset!
 329  *-----------------------------------------------------------------------
 330  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 331  */
 332 #if defined(CONFIG_WATCHDOG)
 333 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 334                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 335 #else
 336 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 337                          SYPCR_SWRI|SYPCR_SWP)
 338 #endif /* CONFIG_WATCHDOG */
 339
 340 /*-----------------------------------------------------------------------
 341  * TMCNTSC - Time Counter Status and Control                     4-40
 342  *-----------------------------------------------------------------------
 343  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 344  * and enable Time Counter
 345  */
 346 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 347
 348 /*-----------------------------------------------------------------------
 349  * PISCR - Periodic Interrupt Status and Control                 4-42
 350  *-----------------------------------------------------------------------
 351  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 352  * Periodic timer
 353  */
 354 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 355
 356 /*-----------------------------------------------------------------------
 357  * SCCR - System Clock Control                                   9-8
 358  *-----------------------------------------------------------------------
 359  * Ensure DFBRG is Divide by 16
 360  */
 361 #define CONFIG_SYS_SCCR        SCCR_DFBRG01
 362
 363 /*-----------------------------------------------------------------------
 364  * RCCR - RISC Controller Configuration                         13-7
 365  *-----------------------------------------------------------------------
 366  */
 367 #define CONFIG_SYS_RCCR        0
 368
 369 #define CONFIG_SYS_MIN_AM_MASK  0xC0000000
 370 /*-----------------------------------------------------------------------
 371  * MPTPR - Memory Refresh Timer Prescaler Register              10-18
 372  *-----------------------------------------------------------------------
 373  */
 374 #define CONFIG_SYS_MPTPR       0x1F00
 375
 376 /*-----------------------------------------------------------------------
 377  * PSRT - Refresh Timer Register                                10-16
 378  *-----------------------------------------------------------------------
 379  */
 380 #define CONFIG_SYS_PSRT        0x0f
 381
 382 /*-----------------------------------------------------------------------
 383  * PSRT - SDRAM Mode Register                                   10-10
 384  *-----------------------------------------------------------------------
 385  */
 386
 387         /* SDRAM initialization values for 8-column chips
 388          */
 389 #define CONFIG_SYS_OR2_8COL     (CONFIG_SYS_MIN_AM_MASK         |\
 390                          ORxS_BPD_4                     |\
 391                          ORxS_ROWST_PBI1_A7             |\
 392                          ORxS_NUMR_12)
 393
 394 #define CONFIG_SYS_PSDMR_8COL   (PSDMR_PBI                      |\
 395                          PSDMR_SDAM_A15_IS_A5           |\
 396                          PSDMR_BSMA_A15_A17             |\
 397                          PSDMR_SDA10_PBI1_A7            |\
 398                          PSDMR_RFRC_7_CLK               |\
 399                          PSDMR_PRETOACT_3W              |\
 400                          PSDMR_ACTTORW_2W               |\
 401                          PSDMR_LDOTOPRE_1C              |\
 402                          PSDMR_WRC_1C                   |\
 403                          PSDMR_CL_2)
 404
 405         /* SDRAM initialization values for 9-column chips
 406          */
 407 #define CONFIG_SYS_OR2_9COL     (CONFIG_SYS_MIN_AM_MASK         |\
 408                          ORxS_BPD_4                     |\
 409                          ORxS_ROWST_PBI1_A6             |\
 410                          ORxS_NUMR_12)
 411
 412 #define CONFIG_SYS_PSDMR_9COL   (PSDMR_PBI                      |\
 413                          PSDMR_SDAM_A16_IS_A5           |\
 414                          PSDMR_BSMA_A15_A17             |\
 415                          PSDMR_SDA10_PBI1_A6            |\
 416                          PSDMR_RFRC_7_CLK               |\
 417                          PSDMR_PRETOACT_3W              |\
 418                          PSDMR_ACTTORW_2W               |\
 419                          PSDMR_LDOTOPRE_1C              |\
 420                          PSDMR_WRC_1C                   |\
 421                          PSDMR_CL_2)
 422
 423 /*
 424  * Init Memory Controller:
 425  *
 426  * Bank Bus     Machine PortSz  Device
 427  * ---- ---     ------- ------  ------
 428  *  0   60x     GPCM    8  bit  Boot ROM
 429  *  1   60x     GPCM    64 bit  FLASH
 430  *  2   60x     SDRAM   64 bit  SDRAM
 431  *
 432  */
 433
 434 #define CONFIG_SYS_MRS_OFFS     0x00000000
 435
 436 /* Bank 0 - FLASH
 437  */
 438 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 439                          BRx_PS_16                      |\
 440                          BRx_MS_GPCM_P                  |\
 441                          BRx_V)
 442
 443 #define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
 444                          ORxG_CSNT                      |\
 445                          ORxG_ACS_DIV1                  |\
 446                          ORxG_SCY_3_CLK                 |\
 447                          ORxU_EHTR_8IDLE)
 448
 449
 450 /* Bank 2 - 60x bus SDRAM
 451  */
 452 #ifndef CONFIG_SYS_RAMBOOT
 453 #define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 454                          BRx_PS_64                      |\
 455                          BRx_MS_SDRAM_P                 |\
 456                          BRx_V)
 457
 458 #define CONFIG_SYS_OR2_PRELIM    CONFIG_SYS_OR2_8COL
 459
 460 #define CONFIG_SYS_PSDMR         CONFIG_SYS_PSDMR_8COL
 461 #endif /* CONFIG_SYS_RAMBOOT */
 462
 463 #define CONFIG_SYS_BR4_PRELIM  ((RTC_BASE_ADDR & BRx_BA_MSK)   |\
 464                          BRx_PS_8                       |\
 465                          BRx_MS_UPMA                    |\
 466                          BRx_V)
 467
 468 #define CONFIG_SYS_OR4_PRELIM  (ORxU_AM_MSK | ORxU_BI)
 469
 470 /*-----------------------------------------------------------------------
 471  * PCMCIA stuff
 472  *-----------------------------------------------------------------------
 473  *
 474  */
 475 #define CONFIG_I82365
 476
 477 #define CONFIG_SYS_PCMCIA_MEM_ADDR      0x81000000
 478 #define CONFIG_SYS_PCMCIA_MEM_SIZE      0x1000
 479
 480 /*-----------------------------------------------------------------------
 481  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 482  *-----------------------------------------------------------------------
 483  */
 484
 485 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 486
 487 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 488 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 489 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 490
 491 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 492 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 493
 494 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 495
 496 #define CONFIG_SYS_ATA_BASE_ADDR        0xa0000000
 497
 498 /* Offset for data I/O                  */
 499 #define CONFIG_SYS_ATA_DATA_OFFSET      0x100
 500
 501 /* Offset for normal register accesses  */
 502 #define CONFIG_SYS_ATA_REG_OFFSET       0x100
 503
 504 /* Offset for alternate registers       */
 505 #define CONFIG_SYS_ATA_ALT_OFFSET       0x108
 506
 507 #endif  /* __CONFIG_H */