include/configs/atstk1002.h

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * Configuration settings for the ATSTK1002 CPU daughterboard
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include <asm/arch/hardware.h>
  12
  13 #define CONFIG_AT32AP
  14 #define CONFIG_AT32AP7000
  15 #define CONFIG_ATSTK1002
  16 #define CONFIG_ATSTK1000
  17
  18 /*
  19  * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
  20  * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
  21  * PLL frequency.
  22  * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
  23  */
  24 #define CONFIG_PLL
  25 #define CONFIG_SYS_POWER_MANAGER
  26 #define CONFIG_SYS_OSC0_HZ                      20000000
  27 #define CONFIG_SYS_PLL0_DIV                     1
  28 #define CONFIG_SYS_PLL0_MUL                     7
  29 #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
  30 /*
  31  * Set the CPU running at:
  32  * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
  33  */
  34 #define CONFIG_SYS_CLKDIV_CPU                   0
  35 /*
  36  * Set the HSB running at:
  37  * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
  38  */
  39 #define CONFIG_SYS_CLKDIV_HSB                   1
  40 /*
  41  * Set the PBA running at:
  42  * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
  43  */
  44 #define CONFIG_SYS_CLKDIV_PBA                   2
  45 /*
  46  * Set the PBB running at:
  47  * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
  48  */
  49 #define CONFIG_SYS_CLKDIV_PBB                   1
  50
  51 /* Reserve VM regions for SDRAM and NOR flash */
  52 #define CONFIG_SYS_NR_VM_REGIONS                2
  53
  54 /*
  55  * The PLLOPT register controls the PLL like this:
  56  *   icp = PLLOPT<2>
  57  *   ivco = PLLOPT<1:0>
  58  *
  59  * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
  60  */
  61 #define CONFIG_SYS_PLL0_OPT                     0x04
  62
  63 #define CONFIG_USART_BASE               ATMEL_BASE_USART1
  64 #define CONFIG_USART_ID                 1
  65
  66 /* User serviceable stuff */
  67 #define CONFIG_DOS_PARTITION
  68
  69 #define CONFIG_CMDLINE_TAG
  70 #define CONFIG_SETUP_MEMORY_TAGS
  71 #define CONFIG_INITRD_TAG
  72
  73 #define CONFIG_STACKSIZE                (2048)
  74
  75 #define CONFIG_BAUDRATE                 115200
  76 #define CONFIG_BOOTARGS                                                 \
  77         "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1"
  78
  79 #define CONFIG_BOOTCOMMAND                                              \
  80         "fsload; bootm $(fileaddr)"
  81
  82 #define CONFIG_BOOTDELAY                1
  83
  84 /*
  85  * After booting the board for the first time, new ethernet addresses
  86  * should be generated and assigned to the environment variables
  87  * "ethaddr" and "eth1addr". This is normally done during production.
  88  */
  89 #define CONFIG_OVERWRITE_ETHADDR_ONCE
  90
  91 /*
  92  * BOOTP options
  93  */
  94 #define CONFIG_BOOTP_SUBNETMASK
  95 #define CONFIG_BOOTP_GATEWAY
  96
  97 /* generic board */
  98 #define CONFIG_BOARD_EARLY_INIT_F
  99 #define CONFIG_BOARD_EARLY_INIT_R
 100
 101 /*
 102  * Command line configuration.
 103  */
 104 #define CONFIG_CMD_ASKENV
 105 #define CONFIG_CMD_DHCP
 106 #define CONFIG_CMD_EXT2
 107 #define CONFIG_CMD_FAT
 108 #define CONFIG_CMD_JFFS2
 109 #define CONFIG_CMD_MMC
 110
 111
 112 #define CONFIG_ATMEL_USART
 113 #define CONFIG_MACB
 114 #define CONFIG_PORTMUX_PIO
 115 #define CONFIG_SYS_NR_PIOS                      5
 116 #define CONFIG_SYS_HSDRAMC
 117 #define CONFIG_MMC
 118 #define CONFIG_GENERIC_ATMEL_MCI
 119 #define CONFIG_GENERIC_MMC
 120
 121 #define CONFIG_SYS_DCACHE_LINESZ                32
 122 #define CONFIG_SYS_ICACHE_LINESZ                32
 123
 124 #define CONFIG_NR_DRAM_BANKS            1
 125
 126 #define CONFIG_SYS_FLASH_CFI
 127 #define CONFIG_FLASH_CFI_DRIVER
 128
 129 #define CONFIG_SYS_FLASH_BASE                   0x00000000
 130 #define CONFIG_SYS_FLASH_SIZE                   0x800000
 131 #define CONFIG_SYS_MAX_FLASH_BANKS              1
 132 #define CONFIG_SYS_MAX_FLASH_SECT               135
 133
 134 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 135 #define CONFIG_SYS_TEXT_BASE            0x00000000
 136
 137 #define CONFIG_SYS_INTRAM_BASE                  INTERNAL_SRAM_BASE
 138 #define CONFIG_SYS_INTRAM_SIZE                  INTERNAL_SRAM_SIZE
 139 #define CONFIG_SYS_SDRAM_BASE                   EBI_SDRAM_BASE
 140
 141 #define CONFIG_ENV_IS_IN_FLASH
 142 #define CONFIG_ENV_SIZE                 65536
 143 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
 144
 145 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
 146
 147 #define CONFIG_SYS_MALLOC_LEN                   (256*1024)
 148
 149 /* Allow 4MB for the kernel run-time image */
 150 #define CONFIG_SYS_LOAD_ADDR                    (EBI_SDRAM_BASE + 0x00400000)
 151 #define CONFIG_SYS_BOOTPARAMS_LEN               (16 * 1024)
 152
 153 /* Other configuration settings that shouldn't have to change all that often */
 154 #define CONFIG_SYS_CBSIZE                       256
 155 #define CONFIG_SYS_MAXARGS                      16
 156 #define CONFIG_SYS_PBSIZE                       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 157 #define CONFIG_SYS_LONGHELP
 158
 159 #define CONFIG_SYS_MEMTEST_START                EBI_SDRAM_BASE
 160 #define CONFIG_SYS_MEMTEST_END                  (CONFIG_SYS_MEMTEST_START + 0x700000)
 161 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 162
 163 #endif /* __CONFIG_H */