include/configs/axs101.h

   1 /*
   2  * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _CONFIG_AXS101_H_
   8 #define _CONFIG_AXS101_H_
   9
  10 /*
  11  *  CPU configuration
  12  */
  13 #define CONFIG_ARC700
  14 #define CONFIG_ARC_MMU_VER              3
  15 #define CONFIG_SYS_CACHELINE_SIZE       32
  16 #define CONFIG_SYS_CLK_FREQ             750000000
  17 #define CONFIG_SYS_TIMER_RATE           CONFIG_SYS_CLK_FREQ
  18
  19 /* NAND controller DMA doesn't work correctly with D$ enabled */
  20 #define CONFIG_SYS_DCACHE_OFF
  21
  22 /*
  23  * Board configuration
  24  */
  25 #define CONFIG_SYS_GENERIC_BOARD
  26 #define CONFIG_SKIP_LOWLEVEL_INIT       /* U-Boot is in RAM already */
  27
  28 #define CONFIG_ARCH_EARLY_INIT_R
  29
  30 #define ARC_FPGA_PERIPHERAL_BASE        0xE0000000
  31 #define ARC_APB_PERIPHERAL_BASE         0xF0000000
  32 #define ARC_DWMMC_BASE                  (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
  33 #define ARC_DWGMAC_BASE                 (ARC_FPGA_PERIPHERAL_BASE + 0x18000)
  34
  35 /*
  36  * Memory configuration
  37  */
  38 #define CONFIG_SYS_TEXT_BASE            0x81000000
  39 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  40
  41 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000
  42 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  43 #define CONFIG_SYS_SDRAM_SIZE           0x20000000      /* 512 Mb */
  44
  45 #define CONFIG_SYS_INIT_SP_ADDR         \
  46         (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
  47
  48 #define CONFIG_SYS_MALLOC_LEN           0x200000        /* 2 MB */
  49 #define CONFIG_SYS_BOOTM_LEN            0x2000000       /* 32 MB */
  50 #define CONFIG_SYS_LOAD_ADDR            0x82000000
  51
  52 /*
  53  * NAND Flash configuration
  54  */
  55 #define CONFIG_SYS_NO_FLASH
  56 #define CONFIG_SYS_NAND_BASE            (ARC_FPGA_PERIPHERAL_BASE + 0x16000)
  57 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  58
  59 /*
  60  * UART configuration
  61  *
  62  * CONFIG_CONS_INDEX = 1 - Debug UART
  63  * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
  64  */
  65 #define CONFIG_CONS_INDEX               4
  66 #define CONFIG_SYS_NS16550
  67 #define CONFIG_SYS_NS16550_SERIAL
  68 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  69 #if (CONFIG_CONS_INDEX == 1)
  70         /* Debug UART */
  71 #       define CONFIG_SYS_NS16550_CLK           33333000
  72 #else
  73         /* FPGA UARTs use different clock */
  74 #       define CONFIG_SYS_NS16550_CLK           33333333
  75 #endif
  76 #define CONFIG_SYS_NS16550_COM1         (ARC_APB_PERIPHERAL_BASE + 0x5000)
  77 #define CONFIG_SYS_NS16550_COM2         (ARC_FPGA_PERIPHERAL_BASE + 0x20000)
  78 #define CONFIG_SYS_NS16550_COM3         (ARC_FPGA_PERIPHERAL_BASE + 0x21000)
  79 #define CONFIG_SYS_NS16550_COM4         (ARC_FPGA_PERIPHERAL_BASE + 0x22000)
  80 #define CONFIG_SYS_NS16550_MEM32
  81
  82 #define CONFIG_BAUDRATE                 115200
  83 /*
  84  * I2C configuration
  85  */
  86 #define CONFIG_SYS_I2C
  87 #define CONFIG_SYS_I2C_DW
  88 #define CONFIG_I2C_ENV_EEPROM_BUS       2
  89 #define CONFIG_SYS_I2C_SPEED            100000
  90 #define CONFIG_SYS_I2C_SPEED1           100000
  91 #define CONFIG_SYS_I2C_SPEED2           100000
  92 #define CONFIG_SYS_I2C_SLAVE            0
  93 #define CONFIG_SYS_I2C_SLAVE1           0
  94 #define CONFIG_SYS_I2C_SLAVE2           0
  95 #define CONFIG_SYS_I2C_BASE             0xE001D000
  96 #define CONFIG_SYS_I2C_BASE1            0xE001E000
  97 #define CONFIG_SYS_I2C_BASE2            0xE001F000
  98 #define CONFIG_SYS_I2C_BUS_MAX          3
  99 #define IC_CLK                          50
 100
 101 /*
 102  * EEPROM configuration
 103  */
 104 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 105 #define CONFIG_SYS_I2C_EEPROM_ADDR              (0xA8 >> 1)
 106 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 107 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     1
 108 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 109 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   64
 110
 111 /*
 112  * SD/MMC configuration
 113  */
 114 #define CONFIG_MMC
 115 #define CONFIG_GENERIC_MMC
 116 #define CONFIG_DWMMC
 117 #define CONFIG_DOS_PARTITION
 118
 119 /*
 120  * Ethernet PHY configuration
 121  */
 122 #define CONFIG_PHYLIB
 123 #define CONFIG_MII
 124 #define CONFIG_PHY_GIGE
 125
 126 /*
 127  * Ethernet configuration
 128  */
 129 #define CONFIG_DESIGNWARE_ETH
 130 #define CONFIG_DW_AUTONEG
 131 #define CONFIG_NET_MULTI
 132
 133 /*
 134  * Command line configuration
 135  */
 136 #include <config_cmd_default.h>
 137
 138 #define CONFIG_CMD_DHCP
 139 #define CONFIG_CMD_EEPROM
 140 #define CONFIG_CMD_ELF
 141 #define CONFIG_CMD_FAT
 142 #define CONFIG_CMD_I2C
 143 #define CONFIG_CMD_MMC
 144 #define CONFIG_CMD_NAND
 145 #define CONFIG_CMD_PING
 146 #define CONFIG_CMD_RARP
 147
 148 #define CONFIG_OF_LIBFDT
 149
 150 #define CONFIG_AUTO_COMPLETE
 151 #define CONFIG_SYS_MAXARGS              16
 152
 153 /*
 154  * Environment settings
 155  */
 156 #define CONFIG_ENV_IS_IN_EEPROM
 157 #define CONFIG_ENV_SIZE                 0x00200         /* 512 bytes */
 158 #define CONFIG_ENV_OFFSET               0
 159
 160 /*
 161  * Environment configuration
 162  */
 163 #define CONFIG_BOOTDELAY                3
 164 #define CONFIG_BOOTFILE                 "uImage"
 165 #define CONFIG_BOOTARGS                 "console=ttyS3,115200n8"
 166 #define CONFIG_LOADADDR                 CONFIG_SYS_LOAD_ADDR
 167
 168 /*
 169  * Console configuration
 170  */
 171 #define CONFIG_SYS_LONGHELP
 172 #define CONFIG_SYS_PROMPT               "AXS# "
 173 #define CONFIG_SYS_CBSIZE               256
 174 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 175 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 176                                                 sizeof(CONFIG_SYS_PROMPT) + 16)
 177
 178 /*
 179  * Misc utility configuration
 180  */
 181 #define CONFIG_BOUNCE_BUFFER
 182
 183 #endif /* _CONFIG_AXS101_H_ */