include/configs/bamboo.h

   1 /*
   2  * (C) Copyright 2005-2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /************************************************************************
  25  * bamboo.h - configuration for BAMBOO board
  26  ***********************************************************************/
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*-----------------------------------------------------------------------
  31  * High Level Configuration Options
  32  *----------------------------------------------------------------------*/
  33 #define CONFIG_BAMBOO           1       /* Board is BAMBOO              */
  34 #define CONFIG_440EP            1       /* Specific PPC440EP support    */
  35 #define CONFIG_440              1       /* ... PPC440 family            */
  36 #define CONFIG_4xx              1       /* ... PPC4xx family            */
  37 #define CONFIG_SYS_CLK_FREQ     33333333    /* external freq to pll     */
  38
  39 #ifndef CONFIG_SYS_TEXT_BASE
  40 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  41 #endif
  42
  43 /*
  44  * Include common defines/options for all AMCC eval boards
  45  */
  46 #define CONFIG_HOSTNAME         bamboo
  47 #include "amcc-common.h"
  48
  49 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  50
  51 /*
  52  * Please note that, if NAND support is enabled, the 2nd ethernet port
  53  * can't be used because of pin multiplexing. So, if you want to use the
  54  * 2nd ethernet port you have to "undef" the following define.
  55  */
  56 #define CONFIG_BAMBOO_NAND      1       /* enable nand flash support    */
  57
  58 /*-----------------------------------------------------------------------
  59  * Base addresses -- Note these are effective addresses where the
  60  * actual resources get mapped (not physical addresses)
  61  *----------------------------------------------------------------------*/
  62 #define CONFIG_SYS_FLASH_BASE           0xfff00000          /* start of FLASH   */
  63 #define CONFIG_SYS_PCI_MEMBASE          0xa0000000          /* mapped pci memory*/
  64 #define CONFIG_SYS_PCI_MEMBASE1        CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  65 #define CONFIG_SYS_PCI_MEMBASE2        CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  66 #define CONFIG_SYS_PCI_MEMBASE3        CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  67
  68 /*Don't change either of these*/
  69 #define CONFIG_SYS_PCI_BASE             0xe0000000          /* internal PCI regs*/
  70 /*Don't change either of these*/
  71
  72 #define CONFIG_SYS_USB_DEVICE          0x50000000
  73 #define CONFIG_SYS_NVRAM_BASE_ADDR     0x80000000
  74 #define CONFIG_SYS_BOOT_BASE_ADDR      0xf0000000
  75 #define CONFIG_SYS_NAND_ADDR           0x90000000
  76 #define CONFIG_SYS_NAND2_ADDR          0x94000000
  77
  78 /*-----------------------------------------------------------------------
  79  * Initial RAM & stack pointer (placed in SDRAM)
  80  *----------------------------------------------------------------------*/
  81 #define CONFIG_SYS_INIT_RAM_DCACHE      1               /* d-cache as init ram  */
  82 #define CONFIG_SYS_INIT_RAM_ADDR        0x70000000      /* DCache       */
  83 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  84 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  85 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  86
  87 /*-----------------------------------------------------------------------
  88  * Serial Port
  89  *----------------------------------------------------------------------*/
  90 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  91 #define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200 /* use external 11.059MHz clk  */
  92
  93 /*-----------------------------------------------------------------------
  94  * NVRAM/RTC
  95  *
  96  * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
  97  * The DS1558 code assumes this condition
  98  *
  99  *----------------------------------------------------------------------*/
 100 #define CONFIG_SYS_NVRAM_SIZE           (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs     */
 101 #define CONFIG_RTC_DS1556       1                        /* DS1556 RTC          */
 102
 103 /*-----------------------------------------------------------------------
 104  * Environment
 105  *----------------------------------------------------------------------*/
 106 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 107 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
 108 #else
 109 #define CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars        */
 110 #define CONFIG_ENV_IS_EMBEDDED  1       /* use embedded environment */
 111 #endif
 112
 113 /*-----------------------------------------------------------------------
 114  * FLASH related
 115  *----------------------------------------------------------------------*/
 116 #define CONFIG_SYS_MAX_FLASH_BANKS      3       /* number of banks                      */
 117 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* sectors per device                   */
 118
 119 #undef  CONFIG_SYS_FLASH_CHECKSUM
 120 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 121 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 122
 123 #define CONFIG_SYS_FLASH_ADDR0         0x555
 124 #define CONFIG_SYS_FLASH_ADDR1         0x2aa
 125 #define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char
 126
 127 #define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1        /* bamboo has 8 and 16bit device        */
 128 #define CONFIG_SYS_FLASH_2ND_ADDR      0x87800000  /* bamboo has 8 and 16bit device     */
 129
 130 #ifdef CONFIG_ENV_IS_IN_FLASH
 131 #define CONFIG_ENV_SECT_SIZE    0x10000 /* size of one complete sector          */
 132 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 133 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 134
 135 /* Address and size of Redundant Environment Sector     */
 136 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 137 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 138 #endif /* CONFIG_ENV_IS_IN_FLASH */
 139
 140 /*
 141  * IPL (Initial Program Loader, integrated inside CPU)
 142  * Will load first 4k from NAND (SPL) into cache and execute it from there.
 143  *
 144  * SPL (Secondary Program Loader)
 145  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 146  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 147  * controller and the NAND controller so that the special U-Boot image can be
 148  * loaded from NAND to SDRAM.
 149  *
 150  * NUB (NAND U-Boot)
 151  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 152  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 153  *
 154  * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 155  * set up. While still running from cache, I experienced problems accessing
 156  * the NAND controller. sr - 2006-08-25
 157  */
 158 #define CONFIG_SYS_NAND_BOOT_SPL_SRC    0xfffff000      /* SPL location                 */
 159 #define CONFIG_SYS_NAND_BOOT_SPL_SIZE   (4 << 10)       /* SPL size                     */
 160 #define CONFIG_SYS_NAND_BOOT_SPL_DST    0x00800000      /* Copy SPL here                */
 161 #define CONFIG_SYS_NAND_U_BOOT_DST      0x01000000      /* Load NUB to this addr        */
 162 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr  */
 163 #define CONFIG_SYS_NAND_BOOT_SPL_DELTA  (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 164
 165 /*
 166  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 167  */
 168 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (16 << 10)      /* Offset to RAM U-Boot image   */
 169 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (384 << 10)     /* Size of RAM U-Boot image     */
 170
 171 /*
 172  * Now the NAND chip has to be defined (no autodetection used!)
 173  */
 174 #define CONFIG_SYS_NAND_PAGE_SIZE       512             /* NAND chip page size          */
 175 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 << 10)      /* NAND chip block size         */
 176 #define CONFIG_SYS_NAND_PAGE_COUNT      32              /* NAND chip page count         */
 177 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   5               /* Location of bad block marker */
 178 #define CONFIG_SYS_NAND_4_ADDR_CYCLE    1               /* Fourth addr used (>32MB)     */
 179
 180 #define CONFIG_SYS_NAND_ECCSIZE 256
 181 #define CONFIG_SYS_NAND_ECCBYTES        3
 182 #define CONFIG_SYS_NAND_OOBSIZE 16
 183 #define CONFIG_SYS_NAND_ECCPOS          {0, 1, 2, 3, 6, 7}
 184
 185 #ifdef CONFIG_ENV_IS_IN_NAND
 186 /*
 187  * For NAND booting the environment is embedded in the U-Boot image. Please take
 188  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 189  */
 190 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 191 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 192 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 193 #endif
 194
 195 /*-----------------------------------------------------------------------
 196  * NAND FLASH
 197  *----------------------------------------------------------------------*/
 198 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 199 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 200 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
 201 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips   */
 202
 203 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 204 #define CONFIG_SYS_NAND_CS              1
 205 #else
 206 #define CONFIG_SYS_NAND_CS              0               /* NAND chip connected to CSx   */
 207 /* Memory Bank 0 (NAND-FLASH) initialization                                    */
 208 #define CONFIG_SYS_EBC_PB0AP            0x018003c0
 209 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 210 #endif
 211
 212 /*-----------------------------------------------------------------------
 213  * DDR SDRAM
 214  *----------------------------------------------------------------------------- */
 215 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
 216 #undef CONFIG_DDR_ECC                   /* don't use ECC                        */
 217 #define CONFIG_SYS_SIMULATE_SPD_EEPROM  0xff    /* simulate spd eeprom on this address  */
 218 #define SPD_EEPROM_ADDRESS      {CONFIG_SYS_SIMULATE_SPD_EEPROM, 0x50, 0x51}
 219 #define CONFIG_SYS_MBYTES_SDRAM (64)    /* 64MB fixed size for early-sdram-init */
 220 #define CONFIG_PROG_SDRAM_TLB
 221
 222 /*-----------------------------------------------------------------------
 223  * I2C
 224  *----------------------------------------------------------------------*/
 225 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 226
 227 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 228 #define CONFIG_SYS_I2C_EEPROM_ADDR      (0xa8>>1)
 229 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 230 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 231 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 232
 233 #ifdef CONFIG_ENV_IS_IN_EEPROM
 234 #define CONFIG_ENV_SIZE         0x200       /* Size of Environment vars */
 235 #define CONFIG_ENV_OFFSET               0x0
 236 #endif /* CONFIG_ENV_IS_IN_EEPROM */
 237
 238 /*
 239  * Default environment variables
 240  */
 241 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 242         CONFIG_AMCC_DEF_ENV                                             \
 243         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 244         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 245         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 246         CONFIG_AMCC_DEF_ENV_NAND_UPD                                    \
 247         "kernel_addr=fff00000\0"                                        \
 248         "ramdisk_addr=fff10000\0"                                       \
 249         ""
 250
 251 #define CONFIG_HAS_ETH0
 252 #define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 253 #define CONFIG_PHY1_ADDR        1
 254
 255 #ifndef CONFIG_BAMBOO_NAND
 256 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 257 #endif /* CONFIG_BAMBOO_NAND */
 258
 259 #ifdef CONFIG_440EP
 260 /* USB */
 261 #define CONFIG_USB_OHCI
 262 #define CONFIG_USB_STORAGE
 263
 264 /*Comment this out to enable USB 1.1 device*/
 265 #define USB_2_0_DEVICE
 266 #endif /*CONFIG_440EP*/
 267
 268 /*
 269  * Commands additional to the ones defined in amcc-common.h
 270  */
 271 #define CONFIG_CMD_DATE
 272 #define CONFIG_CMD_EXT2
 273 #define CONFIG_CMD_FAT
 274 #define CONFIG_CMD_PCI
 275 #define CONFIG_CMD_SDRAM
 276 #define CONFIG_CMD_SNTP
 277 #define CONFIG_CMD_USB
 278
 279 #ifdef CONFIG_BAMBOO_NAND
 280 #define CONFIG_CMD_NAND
 281 #endif
 282
 283 #define CONFIG_SUPPORT_VFAT
 284
 285 /* Partitions */
 286 #define CONFIG_MAC_PARTITION
 287 #define CONFIG_DOS_PARTITION
 288 #define CONFIG_ISO_PARTITION
 289
 290 /*-----------------------------------------------------------------------
 291  * PCI stuff
 292  *-----------------------------------------------------------------------
 293  */
 294 /* General PCI */
 295 #define CONFIG_PCI                      /* include pci support          */
 296 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 297 #undef  CONFIG_PCI_PNP                  /* do (not) pci plug-and-play   */
 298 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 299 #define CONFIG_SYS_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
 300
 301 /* Board-specific PCI */
 302 #define CONFIG_SYS_PCI_TARGET_INIT
 303 #define CONFIG_SYS_PCI_MASTER_INIT
 304
 305 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC */
 306 #define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe   /* Whatever */
 307
 308 #endif  /* __CONFIG_H */