include/configs/bamboo.h

   1 /*
   2  * (C) Copyright 2005-2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /************************************************************************
   9  * bamboo.h - configuration for BAMBOO board
  10  ***********************************************************************/
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*-----------------------------------------------------------------------
  15  * High Level Configuration Options
  16  *----------------------------------------------------------------------*/
  17 #define CONFIG_BAMBOO           1       /* Board is BAMBOO              */
  18 #define CONFIG_440EP            1       /* Specific PPC440EP support    */
  19 #define CONFIG_440              1       /* ... PPC440 family            */
  20 #define CONFIG_4xx              1       /* ... PPC4xx family            */
  21 #define CONFIG_SYS_CLK_FREQ     33333333    /* external freq to pll     */
  22
  23 #ifndef CONFIG_SYS_TEXT_BASE
  24 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  25 #endif
  26
  27 /*
  28  * Include common defines/options for all AMCC eval boards
  29  */
  30 #define CONFIG_HOSTNAME         bamboo
  31 #include "amcc-common.h"
  32
  33 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  34
  35 /*
  36  * Please note that, if NAND support is enabled, the 2nd ethernet port
  37  * can't be used because of pin multiplexing. So, if you want to use the
  38  * 2nd ethernet port you have to "undef" the following define.
  39  */
  40 #define CONFIG_BAMBOO_NAND      1       /* enable nand flash support    */
  41
  42 /*-----------------------------------------------------------------------
  43  * Base addresses -- Note these are effective addresses where the
  44  * actual resources get mapped (not physical addresses)
  45  *----------------------------------------------------------------------*/
  46 #define CONFIG_SYS_FLASH_BASE           0xfff00000          /* start of FLASH   */
  47 #define CONFIG_SYS_PCI_MEMBASE          0xa0000000          /* mapped pci memory*/
  48 #define CONFIG_SYS_PCI_MEMBASE1        CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  49 #define CONFIG_SYS_PCI_MEMBASE2        CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  50 #define CONFIG_SYS_PCI_MEMBASE3        CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  51
  52 /*Don't change either of these*/
  53 #define CONFIG_SYS_PCI_BASE             0xe0000000          /* internal PCI regs*/
  54 /*Don't change either of these*/
  55
  56 #define CONFIG_SYS_USB_DEVICE          0x50000000
  57 #define CONFIG_SYS_NVRAM_BASE_ADDR     0x80000000
  58 #define CONFIG_SYS_BOOT_BASE_ADDR      0xf0000000
  59 #define CONFIG_SYS_NAND_ADDR           0x90000000
  60 #define CONFIG_SYS_NAND2_ADDR          0x94000000
  61
  62 /*-----------------------------------------------------------------------
  63  * Initial RAM & stack pointer (placed in SDRAM)
  64  *----------------------------------------------------------------------*/
  65 #define CONFIG_SYS_INIT_RAM_DCACHE      1               /* d-cache as init ram  */
  66 #define CONFIG_SYS_INIT_RAM_ADDR        0x70000000      /* DCache       */
  67 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  68 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  69 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  70
  71 /*-----------------------------------------------------------------------
  72  * Serial Port
  73  *----------------------------------------------------------------------*/
  74 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  75 #define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200 /* use external 11.059MHz clk  */
  76
  77 /*-----------------------------------------------------------------------
  78  * NVRAM/RTC
  79  *
  80  * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
  81  * The DS1558 code assumes this condition
  82  *
  83  *----------------------------------------------------------------------*/
  84 #define CONFIG_SYS_NVRAM_SIZE           (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs     */
  85 #define CONFIG_RTC_DS1556       1                        /* DS1556 RTC          */
  86
  87 /*-----------------------------------------------------------------------
  88  * Environment
  89  *----------------------------------------------------------------------*/
  90 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  91 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
  92 #else
  93 #define CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars        */
  94 #define CONFIG_ENV_IS_EMBEDDED  1       /* use embedded environment */
  95 #endif
  96
  97 /*-----------------------------------------------------------------------
  98  * FLASH related
  99  *----------------------------------------------------------------------*/
 100 #define CONFIG_SYS_MAX_FLASH_BANKS      3       /* number of banks                      */
 101 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* sectors per device                   */
 102
 103 #undef  CONFIG_SYS_FLASH_CHECKSUM
 104 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 105 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 106
 107 #define CONFIG_SYS_FLASH_ADDR0         0x555
 108 #define CONFIG_SYS_FLASH_ADDR1         0x2aa
 109 #define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char
 110
 111 #define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1        /* bamboo has 8 and 16bit device        */
 112 #define CONFIG_SYS_FLASH_2ND_ADDR      0x87800000  /* bamboo has 8 and 16bit device     */
 113
 114 #ifdef CONFIG_ENV_IS_IN_FLASH
 115 #define CONFIG_ENV_SECT_SIZE    0x10000 /* size of one complete sector          */
 116 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 117 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 118
 119 /* Address and size of Redundant Environment Sector     */
 120 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 121 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 122 #endif /* CONFIG_ENV_IS_IN_FLASH */
 123
 124 /*
 125  * IPL (Initial Program Loader, integrated inside CPU)
 126  * Will load first 4k from NAND (SPL) into cache and execute it from there.
 127  *
 128  * SPL (Secondary Program Loader)
 129  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 130  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 131  * controller and the NAND controller so that the special U-Boot image can be
 132  * loaded from NAND to SDRAM.
 133  *
 134  * NUB (NAND U-Boot)
 135  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 136  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 137  *
 138  * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 139  * set up. While still running from cache, I experienced problems accessing
 140  * the NAND controller. sr - 2006-08-25
 141  */
 142 #define CONFIG_SYS_NAND_BOOT_SPL_SRC    0xfffff000      /* SPL location                 */
 143 #define CONFIG_SYS_NAND_BOOT_SPL_SIZE   (4 << 10)       /* SPL size                     */
 144 #define CONFIG_SYS_NAND_BOOT_SPL_DST    0x00800000      /* Copy SPL here                */
 145 #define CONFIG_SYS_NAND_U_BOOT_DST      0x01000000      /* Load NUB to this addr        */
 146 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr  */
 147 #define CONFIG_SYS_NAND_BOOT_SPL_DELTA  (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 148
 149 /*
 150  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 151  */
 152 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (16 << 10)      /* Offset to RAM U-Boot image   */
 153 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (384 << 10)     /* Size of RAM U-Boot image     */
 154
 155 /*
 156  * Now the NAND chip has to be defined (no autodetection used!)
 157  */
 158 #define CONFIG_SYS_NAND_PAGE_SIZE       512             /* NAND chip page size          */
 159 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 << 10)      /* NAND chip block size         */
 160 #define CONFIG_SYS_NAND_PAGE_COUNT      32              /* NAND chip page count         */
 161 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   5               /* Location of bad block marker */
 162 #define CONFIG_SYS_NAND_4_ADDR_CYCLE    1               /* Fourth addr used (>32MB)     */
 163
 164 #define CONFIG_SYS_NAND_ECCSIZE 256
 165 #define CONFIG_SYS_NAND_ECCBYTES        3
 166 #define CONFIG_SYS_NAND_OOBSIZE 16
 167 #define CONFIG_SYS_NAND_ECCPOS          {0, 1, 2, 3, 6, 7}
 168
 169 #ifdef CONFIG_ENV_IS_IN_NAND
 170 /*
 171  * For NAND booting the environment is embedded in the U-Boot image. Please take
 172  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 173  */
 174 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 175 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 176 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 177 #endif
 178
 179 /*-----------------------------------------------------------------------
 180  * NAND FLASH
 181  *----------------------------------------------------------------------*/
 182 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 183 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 184 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
 185 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips   */
 186
 187 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 188 #define CONFIG_SYS_NAND_CS              1
 189 #else
 190 #define CONFIG_SYS_NAND_CS              0               /* NAND chip connected to CSx   */
 191 /* Memory Bank 0 (NAND-FLASH) initialization                                    */
 192 #define CONFIG_SYS_EBC_PB0AP            0x018003c0
 193 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 194 #endif
 195
 196 /*-----------------------------------------------------------------------
 197  * DDR SDRAM
 198  *----------------------------------------------------------------------------- */
 199 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
 200 #undef CONFIG_DDR_ECC                   /* don't use ECC                        */
 201 #define CONFIG_SYS_SIMULATE_SPD_EEPROM  0xff    /* simulate spd eeprom on this address  */
 202 #define SPD_EEPROM_ADDRESS      {CONFIG_SYS_SIMULATE_SPD_EEPROM, 0x50, 0x51}
 203 #define CONFIG_SYS_MBYTES_SDRAM (64)    /* 64MB fixed size for early-sdram-init */
 204 #define CONFIG_PROG_SDRAM_TLB
 205
 206 /*-----------------------------------------------------------------------
 207  * I2C
 208  *----------------------------------------------------------------------*/
 209 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 210
 211 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 212 #define CONFIG_SYS_I2C_EEPROM_ADDR      (0xa8>>1)
 213 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 214 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 215 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 216
 217 #ifdef CONFIG_ENV_IS_IN_EEPROM
 218 #define CONFIG_ENV_SIZE         0x200       /* Size of Environment vars */
 219 #define CONFIG_ENV_OFFSET               0x0
 220 #endif /* CONFIG_ENV_IS_IN_EEPROM */
 221
 222 /*
 223  * Default environment variables
 224  */
 225 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 226         CONFIG_AMCC_DEF_ENV                                             \
 227         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 228         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 229         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 230         CONFIG_AMCC_DEF_ENV_NAND_UPD                                    \
 231         "kernel_addr=fff00000\0"                                        \
 232         "ramdisk_addr=fff10000\0"                                       \
 233         ""
 234
 235 #define CONFIG_HAS_ETH0
 236 #define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 237 #define CONFIG_PHY1_ADDR        1
 238
 239 #ifndef CONFIG_BAMBOO_NAND
 240 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 241 #endif /* CONFIG_BAMBOO_NAND */
 242
 243 #ifdef CONFIG_440EP
 244 /* USB */
 245 #define CONFIG_USB_OHCI
 246 #define CONFIG_USB_STORAGE
 247
 248 /*Comment this out to enable USB 1.1 device*/
 249 #define USB_2_0_DEVICE
 250 #endif /*CONFIG_440EP*/
 251
 252 /*
 253  * Commands additional to the ones defined in amcc-common.h
 254  */
 255 #define CONFIG_CMD_DATE
 256 #define CONFIG_CMD_EXT2
 257 #define CONFIG_CMD_FAT
 258 #define CONFIG_CMD_PCI
 259 #define CONFIG_CMD_SDRAM
 260 #define CONFIG_CMD_SNTP
 261 #define CONFIG_CMD_USB
 262
 263 #ifdef CONFIG_BAMBOO_NAND
 264 #define CONFIG_CMD_NAND
 265 #endif
 266
 267 #define CONFIG_SUPPORT_VFAT
 268
 269 /* Partitions */
 270 #define CONFIG_MAC_PARTITION
 271 #define CONFIG_DOS_PARTITION
 272 #define CONFIG_ISO_PARTITION
 273
 274 /*-----------------------------------------------------------------------
 275  * PCI stuff
 276  *-----------------------------------------------------------------------
 277  */
 278 /* General PCI */
 279 #define CONFIG_PCI                      /* include pci support          */
 280 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 281 #undef  CONFIG_PCI_PNP                  /* do (not) pci plug-and-play   */
 282 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 283 #define CONFIG_SYS_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
 284
 285 /* Board-specific PCI */
 286 #define CONFIG_SYS_PCI_TARGET_INIT
 287 #define CONFIG_SYS_PCI_MASTER_INIT
 288
 289 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC */
 290 #define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe   /* Whatever */
 291
 292 #endif  /* __CONFIG_H */