include/configs/bf525-ucr2.h

   1 /*
   2  * U-Boot - Configuration file for bf525-ucr2 board
   3  * The board includes ADSP-BF525 rev. 0.2,
   4  * 32-bit SDRAM (SAMSUNG K4S561632H-UC75),
   5  * USB 2.0 High Speed OTG USB WIFI,
   6  * SPI flash (cFeon EN25Q128 16 MB),
   7  * Support PPI and ITU-R656,
   8  * See http://www.ucrobotics.com/?q=cn/ucr2
   9  */
  10
  11 #ifndef __CONFIG_BF525_UCR2_H__
  12 #define __CONFIG_BF525_UCR2_H__
  13
  14 #include <asm/config-pre.h>
  15
  16 /*
  17  * Processor Settings
  18  */
  19 #define CONFIG_BFIN_CPU             bf525-0.2
  20 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
  21
  22 /*
  23  * Clock Settings
  24  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
  25  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  26  */
  27 /* CONFIG_CLKIN_HZ is any value in Hz                                   */
  28 #define CONFIG_CLKIN_HZ                 24000000
  29 /* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
  30 /*                                                1 = CLKIN / 2         */
  31 #define CONFIG_CLKIN_HALF               0
  32 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
  33 /*                                                1 = bypass PLL        */
  34 #define CONFIG_PLL_BYPASS               0
  35 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
  36 /* Values can range from 0-63 (where 0 means 64)                        */
  37 #define CONFIG_VCO_MULT                 20
  38 /* CCLK_DIV controls the core clock divider                             */
  39 /* Values can be 1, 2, 4, or 8 ONLY                                     */
  40 #define CONFIG_CCLK_DIV                 1
  41 /* SCLK_DIV controls the system clock divider                           */
  42 /* Values can range from 1-15                                           */
  43 #define CONFIG_SCLK_DIV                 4
  44
  45 /*
  46  * Memory Settings
  47  */
  48 #define CONFIG_MEM_ADD_WDTH     9
  49 #define CONFIG_MEM_SIZE         32
  50
  51 /*
  52  * SDRAM reference page
  53  * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
  54  */
  55 #define CONFIG_EBIU_SDRRC_VAL   0x3f8
  56 #define CONFIG_EBIU_SDGCTL_VAL  0x9111cd
  57
  58 #define CONFIG_EBIU_AMGCTL_VAL  (AMBEN_ALL)
  59 #define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
  60 #define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
  61
  62 #define CONFIG_SYS_MONITOR_LEN  (320 * 1024)
  63 #define CONFIG_SYS_MALLOC_LEN   (320 * 1024)
  64
  65 /* support for serial flash */
  66 #define CONFIG_BFIN_SPI
  67 #define CONFIG_SF_DEFAULT_HZ    30000000
  68
  69 #define CONFIG_ENV_IS_IN_SPI_FLASH
  70 #define CONFIG_ENV_SPI_MAX_HZ   30000000
  71 #define CONFIG_ENV_OFFSET       0x10000
  72 #define CONFIG_ENV_SIZE         0x10000
  73 #define CONFIG_ENV_SECT_SIZE    0x10000
  74 #define CONFIG_ENV_OVERWRITE    1
  75
  76 /*
  77  * Misc Settings
  78  */
  79 #define CONFIG_UART_CONSOLE     0
  80
  81 #define CONFIG_BAUDRATE         115200
  82 #define CONFIG_BFIN_SERIAL
  83 #define CONFIG_BOOTARGS         "root=/dev/mtdblock0 rw"
  84 #define CONFIG_BOOTCOMMAND      "run sfboot"
  85 #define CONFIG_EXTRA_ENV_SETTINGS \
  86         "sfboot=sf probe 1;" \
  87                 "sf read 0x1000000 0x20000 0x300000;" \
  88                 "bootm 0x1000000\0"
  89
  90 #endif