include/configs/bf527-sdp.h

   1 /*
   2  * U-Boot - Configuration file for BF527 SDP board
   3  */
   4
   5 #ifndef __CONFIG_BF527_SDP_H__
   6 #define __CONFIG_BF527_SDP_H__
   7
   8 #include <asm/config-pre.h>
   9
  10 /*
  11  * Processor Settings
  12  */
  13 #define CONFIG_BFIN_CPU             bf527-0.2
  14 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
  15
  16 /*
  17  * Clock Settings
  18  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
  19  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  20  */
  21 /* CONFIG_CLKIN_HZ is any value in Hz                                   */
  22 #define CONFIG_CLKIN_HZ                 24000000
  23 /* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
  24 /*                                                1 = CLKIN / 2         */
  25 #define CONFIG_CLKIN_HALF               0
  26 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
  27 /*                                                1 = bypass PLL        */
  28 #define CONFIG_PLL_BYPASS               0
  29 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
  30 /* Values can range from 0-63 (where 0 means 64)                        */
  31 #define CONFIG_VCO_MULT                 25
  32 /* CCLK_DIV controls the core clock divider                             */
  33 /* Values can be 1, 2, 4, or 8 ONLY                                     */
  34 #define CONFIG_CCLK_DIV                 1
  35 /* SCLK_DIV controls the system clock divider                           */
  36 /* Values can range from 1-15                                           */
  37 #define CONFIG_SCLK_DIV                 5
  38
  39 #define CONFIG_PLL_LOCKCNT_VAL  0x0200
  40 #define CONFIG_PLL_CTL_VAL              0x2a00
  41 #define CONFIG_VR_CTL_VAL               0x7090
  42
  43 /*
  44  * Memory Settings
  45  */
  46 #define CONFIG_MEM_ADD_WDTH     9
  47 #define CONFIG_MEM_SIZE         32
  48
  49 #define CONFIG_EBIU_SDRRC_VAL   0x00FE
  50 #define CONFIG_EBIU_SDGCTL_VAL  0x8011998d
  51
  52 #define CONFIG_EBIU_AMGCTL_VAL  (AMCKEN | AMBEN_ALL)
  53 #define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
  54 #define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
  55
  56 #define CONFIG_SYS_MONITOR_LEN  (768 * 1024)
  57 #define CONFIG_SYS_MALLOC_LEN   (640 * 1024)
  58
  59 /*
  60  * Flash Settings
  61  */
  62 #define CONFIG_FLASH_CFI_DRIVER
  63 #define CONFIG_SYS_FLASH_BASE           0x20000000
  64 #define CONFIG_SYS_FLASH_CFI
  65 #define CONFIG_SYS_FLASH_PROTECTION
  66 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  67 #define CONFIG_SYS_MAX_FLASH_SECT       259
  68
  69 /*
  70  * SPI Settings
  71  */
  72 #define CONFIG_BFIN_SPI
  73 #define CONFIG_ENV_SPI_MAX_HZ   30000000
  74 #define CONFIG_SF_DEFAULT_SPEED 30000000
  75 #define CONFIG_SPI_FLASH_ALL
  76
  77 /*
  78  * Env Storage Settings
  79  */
  80 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
  81 #define CONFIG_ENV_IS_IN_SPI_FLASH
  82 #define CONFIG_ENV_OFFSET       0x10000
  83 #define CONFIG_ENV_SIZE         0x2000
  84 #define CONFIG_ENV_SECT_SIZE    0x10000
  85 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
  86 #else
  87 #define CONFIG_ENV_IS_IN_FLASH
  88 #define CONFIG_ENV_OFFSET       0x4000
  89 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
  90 #define CONFIG_ENV_SIZE         0x2000
  91 #define CONFIG_ENV_SECT_SIZE    0x2000
  92 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
  93 #endif
  94
  95 /*
  96  * I2C Settings
  97  */
  98 #define CONFIG_SYS_I2C
  99 #define CONFIG_SYS_I2C_ADI
 100
 101 /*
 102  * Misc Settings
 103  */
 104 #define CONFIG_MISC_INIT_R
 105 #define CONFIG_UART_CONSOLE     0
 106
 107 /*
 108  * Pull in common ADI header for remaining command/environment setup
 109  */
 110 #include <configs/bfin_adi_common.h>
 111
 112 #endif