include/configs/bf533-stamp.h

   1 /*
   2  * U-Boot - Configuration file for BF533 STAMP board
   3  */
   4
   5 #ifndef __CONFIG_BF533_STAMP_H__
   6 #define __CONFIG_BF533_STAMP_H__
   7
   8 #include <asm/config-pre.h>
   9
  10 /*
  11  * Processor Settings
  12  */
  13 #define CONFIG_BFIN_CPU             bf533-0.3
  14 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
  15
  16 /*
  17  * Clock Settings
  18  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
  19  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  20  */
  21 /* CONFIG_CLKIN_HZ is any value in Hz                                   */
  22 #define CONFIG_CLKIN_HZ                 11059200
  23 /* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
  24 /*                                                1 = CLKIN / 2         */
  25 #define CONFIG_CLKIN_HALF               0
  26 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
  27 /*                                                1 = bypass PLL        */
  28 #define CONFIG_PLL_BYPASS               0
  29 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
  30 /* Values can range from 0-63 (where 0 means 64)                        */
  31 #define CONFIG_VCO_MULT                 45
  32 /* CCLK_DIV controls the core clock divider                             */
  33 /* Values can be 1, 2, 4, or 8 ONLY                                     */
  34 #define CONFIG_CCLK_DIV                 1
  35 /* SCLK_DIV controls the system clock divider                           */
  36 /* Values can range from 1-15                                           */
  37 #define CONFIG_SCLK_DIV                 6 /* note: 1.2 boards can go faster */
  38
  39 /*
  40  * Memory Settings
  41  */
  42 #define CONFIG_MEM_ADD_WDTH     11
  43 #define CONFIG_MEM_SIZE         128
  44
  45 #define CONFIG_EBIU_SDRRC_VAL   0x268
  46 #define CONFIG_EBIU_SDGCTL_VAL  0x911109
  47
  48 #define CONFIG_EBIU_AMGCTL_VAL  0xFF
  49 #define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
  50 #define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
  51
  52 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)
  53 #define CONFIG_SYS_MALLOC_LEN   (384 * 1024)
  54
  55 /*
  56  * Network Settings
  57  */
  58 #define ADI_CMDS_NETWORK        1
  59 #define CONFIG_SMC91111 1
  60 #define CONFIG_SMC91111_BASE    0x20300300
  61 #define SMC91111_EEPROM_INIT() \
  62         do { \
  63                 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
  64                 bfin_write_FIO_FLAG_C(PF1); \
  65                 bfin_write_FIO_FLAG_S(PF0); \
  66                 SSYNC(); \
  67         } while (0)
  68 #define CONFIG_HOSTNAME         bf533-stamp
  69
  70 /* I2C */
  71 #define CONFIG_SYS_I2C
  72 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
  73 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
  74 #define CONFIG_SYS_I2C_SOFT_SLAVE       0
  75 /*
  76  * Software (bit-bang) I2C driver configuration
  77  */
  78 #define CONFIG_SOFT_I2C_GPIO_SCL        GPIO_PF3
  79 #define CONFIG_SOFT_I2C_GPIO_SDA        GPIO_PF2
  80
  81 /*
  82  * Flash Settings
  83  */
  84 #define CONFIG_FLASH_CFI_DRIVER
  85 #define CONFIG_SYS_FLASH_BASE           0x20000000
  86 #define CONFIG_SYS_FLASH_CFI
  87 #define CONFIG_SYS_FLASH_CFI_AMD_RESET
  88 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  89 #define CONFIG_SYS_MAX_FLASH_SECT       67
  90
  91 /*
  92  * SPI Settings
  93  */
  94 #define CONFIG_BFIN_SPI
  95 #define CONFIG_ENV_SPI_MAX_HZ   30000000
  96 /*
  97 #define CONFIG_SF_DEFAULT_SPEED 30000000
  98 #define CONFIG_SPI_FLASH_ALL
  99 */
 100
 101 /*
 102  * Env Storage Settings
 103  */
 104 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
 105 #define CONFIG_ENV_IS_IN_SPI_FLASH
 106 #define CONFIG_ENV_OFFSET       0x10000
 107 #define CONFIG_ENV_SIZE         0x2000
 108 #define CONFIG_ENV_SECT_SIZE    0x10000
 109 #else
 110 #define CONFIG_ENV_IS_IN_FLASH
 111 #define CONFIG_ENV_OFFSET       0x4000
 112 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 113 #define CONFIG_ENV_SIZE         0x2000
 114 #define CONFIG_ENV_SECT_SIZE    0x2000
 115 #endif
 116 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
 117 #define ENV_IS_EMBEDDED
 118 #else
 119 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 120 #endif
 121 #ifdef ENV_IS_EMBEDDED
 122 /* WARNING - the following is hand-optimized to fit within
 123  * the sector before the environment sector. If it throws
 124  * an error during compilation remove an object here to get
 125  * it linked after the configuration sector.
 126  */
 127 # define LDS_BOARD_TEXT \
 128         arch/blackfin/lib/built-in.o (.text*); \
 129         arch/blackfin/cpu/built-in.o (.text*); \
 130         . = DEFINED(env_offset) ? env_offset : .; \
 131         common/env_embedded.o (.text*);
 132 #endif
 133
 134 /*
 135  * I2C Settings
 136  */
 137 #define CONFIG_SYS_I2C_SOFT
 138 #ifdef CONFIG_SYS_I2C_SOFT
 139 #define CONFIG_SYS_I2C
 140 #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
 141 #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
 142 #define I2C_DELAY               udelay(5)       /* 1/4 I2C clock duration */
 143 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
 144 #define CONFIG_SYS_I2C_SOFT_SLAVE       0
 145 #endif
 146
 147 /*
 148  * Compact Flash / IDE / ATA Settings
 149  */
 150
 151 /* Enabled below option for CF support */
 152 /* #define CONFIG_STAMP_CF */
 153 #if defined(CONFIG_STAMP_CF)
 154 #define CONFIG_MISC_INIT_R
 155 #define CONFIG_DOS_PARTITION    1
 156 #undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
 157 #undef  CONFIG_IDE_LED                  /* no led for ide supported */
 158 #undef  CONFIG_IDE_RESET                /* no reset for ide supported */
 159
 160 #define CONFIG_SYS_IDE_MAXBUS           1
 161 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS * 1)
 162
 163 #define CONFIG_SYS_ATA_BASE_ADDR        0x20200000
 164 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 165
 166 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0020  /* data I/O */
 167 #define CONFIG_SYS_ATA_REG_OFFSET       0x0020  /* normal register accesses */
 168 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0007  /* alternate registers */
 169
 170 #define CONFIG_SYS_ATA_STRIDE           2
 171
 172 #undef CONFIG_EBIU_AMBCTL1_VAL
 173 #define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
 174 #endif
 175
 176 /*
 177  * Misc Settings
 178  */
 179 #define CONFIG_RTC_BFIN
 180 #define CONFIG_UART_CONSOLE     0
 181
 182 /* FLASH/ETHERNET uses the same async bank */
 183 #define SHARED_RESOURCES        1
 184
 185 /* define to enable boot progress via leds */
 186 /* #define CONFIG_SHOW_BOOT_PROGRESS */
 187
 188 /* define to enable run status via led */
 189 /* #define CONFIG_STATUS_LED */
 190 #ifdef CONFIG_STATUS_LED
 191 #define CONFIG_GPIO_LED
 192 #define CONFIG_BOARD_SPECIFIC_LED
 193 /* use LED0 to indicate booting/alive */
 194 #define STATUS_LED_BOOT 0
 195 #define STATUS_LED_BIT GPIO_PF2
 196 #define STATUS_LED_STATE STATUS_LED_ON
 197 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
 198 /* use LED1 to indicate crash */
 199 #define STATUS_LED_CRASH 1
 200 #define STATUS_LED_BIT1 GPIO_PF3
 201 #define STATUS_LED_STATE1 STATUS_LED_ON
 202 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
 203 /* #define STATUS_LED_BIT2 GPIO_PF4 */
 204 #endif
 205
 206 /* define to enable splash screen support */
 207
 208 /*
 209  * Pull in common ADI header for remaining command/environment setup
 210  */
 211 #include <configs/bfin_adi_common.h>
 212
 213 #endif