include/configs/bf537-stamp.h

   1 /*
   2  * U-Boot - Configuration file for BF537 STAMP board
   3  */
   4
   5 #ifndef __CONFIG_BF537_STAMP_H__
   6 #define __CONFIG_BF537_STAMP_H__
   7
   8 #include <asm/config-pre.h>
   9
  10 /*
  11  * Processor Settings
  12  */
  13 #define CONFIG_BFIN_CPU             bf537-0.2
  14 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
  15
  16 /*
  17  * Clock Settings
  18  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
  19  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  20  */
  21 /* CONFIG_CLKIN_HZ is any value in Hz                                   */
  22 #define CONFIG_CLKIN_HZ                 25000000
  23 /* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
  24 /*                                                1 = CLKIN / 2         */
  25 #define CONFIG_CLKIN_HALF               0
  26 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
  27 /*                                                1 = bypass PLL        */
  28 #define CONFIG_PLL_BYPASS               0
  29 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
  30 /* Values can range from 0-63 (where 0 means 64)                        */
  31 #define CONFIG_VCO_MULT                 20
  32 /* CCLK_DIV controls the core clock divider                             */
  33 /* Values can be 1, 2, 4, or 8 ONLY                                     */
  34 #define CONFIG_CCLK_DIV                 1
  35 /* SCLK_DIV controls the system clock divider                           */
  36 /* Values can range from 1-15                                           */
  37 #define CONFIG_SCLK_DIV                 4
  38
  39 /*
  40  * Memory Settings
  41  */
  42 #define CONFIG_MEM_ADD_WDTH     10
  43 #define CONFIG_MEM_SIZE         64
  44
  45 #define CONFIG_EBIU_SDRRC_VAL   0x306
  46 #define CONFIG_EBIU_SDGCTL_VAL  0x91114d
  47
  48 #define CONFIG_EBIU_AMGCTL_VAL  0xFF
  49 #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
  50 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
  51
  52 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  53 #define CONFIG_SYS_MALLOC_LEN           (384 * 1024)
  54
  55 /*
  56  * Network Settings
  57  */
  58 #ifndef __ADSPBF534__
  59 #define ADI_CMDS_NETWORK        1
  60 #define CONFIG_BFIN_MAC
  61 #define CONFIG_NETCONSOLE       1
  62 #endif
  63 #define CONFIG_HOSTNAME         bf537-stamp
  64
  65 /*
  66  * Flash Settings
  67  */
  68 #define CONFIG_FLASH_CFI_DRIVER
  69 #define CONFIG_SYS_FLASH_BASE           0x20000000
  70 #define CONFIG_SYS_FLASH_CFI
  71 #define CONFIG_SYS_FLASH_PROTECTION
  72 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  73 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
  74 #define CONFIG_SYS_MAX_FLASH_SECT       71
  75
  76 /*
  77  * SPI Settings
  78  */
  79 #define CONFIG_BFIN_SPI
  80 #define CONFIG_ENV_SPI_MAX_HZ   30000000
  81 #define CONFIG_SF_DEFAULT_SPEED 30000000
  82 #define CONFIG_SPI_FLASH_ALL
  83
  84 /*
  85  * Env Storage Settings
  86  */
  87 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
  88 #define CONFIG_ENV_IS_IN_SPI_FLASH
  89 #define CONFIG_ENV_OFFSET       0x10000
  90 #define CONFIG_ENV_SIZE         0x2000
  91 #define CONFIG_ENV_SECT_SIZE    0x10000
  92 #else
  93 #define CONFIG_ENV_IS_IN_FLASH
  94 #define CONFIG_ENV_OFFSET       0x4000
  95 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
  96 #define CONFIG_ENV_SIZE         0x2000
  97 #define CONFIG_ENV_SECT_SIZE    0x2000
  98 #endif
  99 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
 100 #define ENV_IS_EMBEDDED
 101 #else
 102 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 103 #endif
 104 #ifdef ENV_IS_EMBEDDED
 105 /* WARNING - the following is hand-optimized to fit within
 106  * the sector before the environment sector. If it throws
 107  * an error during compilation remove an object here to get
 108  * it linked after the configuration sector.
 109  */
 110 # define LDS_BOARD_TEXT \
 111         arch/blackfin/lib/built-in.o (.text*); \
 112         arch/blackfin/cpu/built-in.o (.text*); \
 113         . = DEFINED(env_offset) ? env_offset : .; \
 114         common/env_embedded.o (.text*);
 115 #endif
 116
 117 /*
 118  * I2C Settings
 119  */
 120 #define CONFIG_SYS_I2C
 121 #define CONFIG_SYS_I2C_ADI
 122
 123 /*
 124  * SPI_MMC Settings
 125  */
 126 #define CONFIG_MMC_SPI
 127 #ifdef CONFIG_MMC_SPI
 128 #define CONFIG_GENERIC_MMC
 129 #endif
 130
 131 /*
 132  * NAND Settings
 133  */
 134 /* #define CONFIG_NAND_PLAT */
 135 #ifdef CONFIG_NAND_PLAT
 136 #define CONFIG_SYS_NAND_BASE            0x20212000
 137 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 138
 139 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 140 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
 141 #define BFIN_NAND_WRITE(addr, cmd) \
 142         do { \
 143                 bfin_write8(addr, cmd); \
 144                 SSYNC(); \
 145         } while (0)
 146
 147 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 148 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
 149 #define NAND_PLAT_GPIO_DEV_READY       GPIO_PF3
 150 #endif /* CONFIG_NAND_PLAT */
 151
 152 /*
 153  * CF-CARD IDE-HDD Support
 154  */
 155
 156 /*
 157  * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card)
 158  * Strange address mapping Blackfin A13 connects to CF_A0
 159  */
 160
 161 /* #define CONFIG_BFIN_TRUE_IDE */
 162
 163 /*
 164  * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card)
 165  * This should be the preferred mode
 166  */
 167
 168 /* #define CONFIG_BFIN_CF_IDE */
 169
 170 /*
 171  * Add IDE Disk Drive (HDD) support
 172  * See example interface here:
 173  * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin
 174  */
 175
 176 /* #define CONFIG_BFIN_HDD_IDE */
 177
 178 #if defined(CONFIG_BFIN_CF_IDE) || \
 179     defined(CONFIG_BFIN_HDD_IDE) || \
 180     defined(CONFIG_BFIN_TRUE_IDE)
 181 # define CONFIG_BFIN_IDE        1
 182 # define CONFIG_CMD_IDE
 183 #endif
 184
 185 #if defined(CONFIG_BFIN_IDE)
 186
 187 #define CONFIG_DOS_PARTITION    1
 188 /*
 189  * IDE/ATA stuff
 190  */
 191 #undef  CONFIG_IDE_8xx_DIRECT   /* no pcmcia interface required */
 192 #undef  CONFIG_IDE_LED          /* no led for ide supported */
 193 #undef  CONFIG_IDE_RESET        /* no reset for ide supported */
 194
 195 #define CONFIG_SYS_IDE_MAXBUS           1
 196 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS * 1)
 197
 198 #undef  CONFIG_EBIU_AMBCTL1_VAL
 199 #define CONFIG_EBIU_AMBCTL1_VAL         0xFFC3FFC3
 200
 201 #define CONFIG_CF_ATASEL_DIS    0x20311800
 202 #define CONFIG_CF_ATASEL_ENA    0x20311802
 203
 204 #if defined(CONFIG_BFIN_TRUE_IDE)
 205 /*
 206  * Note that these settings aren't for the most part used in include/ata.h
 207  * when all of the ATA registers are setup
 208  */
 209 #define CONFIG_SYS_ATA_BASE_ADDR        0x2031C000
 210 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 211 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0020  /* data I/O */
 212 #define CONFIG_SYS_ATA_REG_OFFSET       0x0020  /* normal register accesses */
 213 #define CONFIG_SYS_ATA_ALT_OFFSET       0x001C  /* alternate registers */
 214 #define CONFIG_SYS_ATA_STRIDE           2       /* CF.A0 --> Blackfin.A13 */
 215
 216 #elif defined(CONFIG_BFIN_CF_IDE)
 217 #define CONFIG_SYS_ATA_BASE_ADDR        0x20211800
 218 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 219 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* data I/O */
 220 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* normal register accesses */
 221 #define CONFIG_SYS_ATA_ALT_OFFSET       0x000E  /* alternate registers */
 222 #define CONFIG_SYS_ATA_STRIDE           1       /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */
 223
 224 #elif defined(CONFIG_BFIN_HDD_IDE)
 225 #define CONFIG_SYS_ATA_BASE_ADDR        0x20314000
 226 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 227 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0020  /* data I/O */
 228 #define CONFIG_SYS_ATA_REG_OFFSET       0x0020  /* normal register accesses */
 229 #define CONFIG_SYS_ATA_ALT_OFFSET       0x001C  /* alternate registers */
 230 #define CONFIG_SYS_ATA_STRIDE           2       /* CF.A0 --> Blackfin.A1 */
 231 #undef  CONFIG_SCLK_DIV
 232 #define CONFIG_SCLK_DIV         8
 233 #endif
 234
 235 #endif
 236
 237 /*
 238  * Misc Settings
 239  */
 240 #define CONFIG_MISC_INIT_R
 241 #define CONFIG_RTC_BFIN
 242 #define CONFIG_UART_CONSOLE     0
 243
 244 /* Define if want to do post memory test */
 245 #undef CONFIG_POST
 246 #ifdef CONFIG_POST
 247 #define CONFIG_SYS_POST_HOTKEYS_GPIO    GPIO_PF5
 248 #define CONFIG_POST_BSPEC1_GPIO_LEDS \
 249         GPIO_PF6, GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11,
 250 #define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
 251         GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2,
 252 #define CONFIG_POST_BSPEC2_GPIO_NAMES \
 253         10, 11, 12, 13,
 254 #define CONFIG_SYS_POST_FLASH_START     11
 255 #define CONFIG_SYS_POST_FLASH_END       71
 256 #endif
 257
 258 /* These are for board tests */
 259 #if 0
 260 #define CONFIG_BOOTCOMMAND       "bootldr 0x203f0100"
 261 #endif
 262
 263 /*
 264  * Pull in common ADI header for remaining command/environment setup
 265  */
 266 #include <configs/bfin_adi_common.h>
 267
 268 #endif