include/configs/bf537-stamp.h

   1 /*
   2  * U-boot - Configuration file for BF537 STAMP board
   3  */
   4
   5 #ifndef __CONFIG_BF537_STAMP_H__
   6 #define __CONFIG_BF537_STAMP_H__
   7
   8 #include <asm/config-pre.h>
   9
  10
  11 /*
  12  * Processor Settings
  13  */
  14 #define CONFIG_BFIN_CPU             bf537-0.2
  15 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
  16
  17
  18 /*
  19  * Clock Settings
  20  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
  21  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  22  */
  23 /* CONFIG_CLKIN_HZ is any value in Hz                                   */
  24 #define CONFIG_CLKIN_HZ                 25000000
  25 /* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
  26 /*                                                1 = CLKIN / 2         */
  27 #define CONFIG_CLKIN_HALF               0
  28 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
  29 /*                                                1 = bypass PLL        */
  30 #define CONFIG_PLL_BYPASS               0
  31 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
  32 /* Values can range from 0-63 (where 0 means 64)                        */
  33 #define CONFIG_VCO_MULT                 20
  34 /* CCLK_DIV controls the core clock divider                             */
  35 /* Values can be 1, 2, 4, or 8 ONLY                                     */
  36 #define CONFIG_CCLK_DIV                 1
  37 /* SCLK_DIV controls the system clock divider                           */
  38 /* Values can range from 1-15                                           */
  39 #define CONFIG_SCLK_DIV                 4
  40
  41
  42 /*
  43  * Memory Settings
  44  */
  45 #define CONFIG_MEM_ADD_WDTH     10
  46 #define CONFIG_MEM_SIZE         64
  47
  48 #define CONFIG_EBIU_SDRRC_VAL   0x306
  49 #define CONFIG_EBIU_SDGCTL_VAL  0x91114d
  50
  51 #define CONFIG_EBIU_AMGCTL_VAL  0xFF
  52 #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
  53 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
  54
  55 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
  56 #define CONFIG_SYS_MALLOC_LEN           (384 * 1024)
  57
  58
  59 /*
  60  * Network Settings
  61  */
  62 #ifndef __ADSPBF534__
  63 #define ADI_CMDS_NETWORK        1
  64 #define CONFIG_BFIN_MAC
  65 #define CONFIG_NETCONSOLE       1
  66 #define CONFIG_NET_MULTI        1
  67 #endif
  68 #define CONFIG_HOSTNAME         bf537-stamp
  69 /* Uncomment next line to use fixed MAC address */
  70 /* #define CONFIG_ETHADDR       02:80:ad:20:31:e8 */
  71
  72
  73 /*
  74  * Flash Settings
  75  */
  76 #define CONFIG_FLASH_CFI_DRIVER
  77 #define CONFIG_SYS_FLASH_BASE           0x20000000
  78 #define CONFIG_SYS_FLASH_CFI
  79 #define CONFIG_SYS_FLASH_PROTECTION
  80 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  81 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
  82 #define CONFIG_SYS_MAX_FLASH_SECT       71
  83
  84
  85 /*
  86  * SPI Settings
  87  */
  88 #define CONFIG_BFIN_SPI
  89 #define CONFIG_ENV_SPI_MAX_HZ   30000000
  90 #define CONFIG_SF_DEFAULT_SPEED 30000000
  91 #define CONFIG_SPI_FLASH
  92 #define CONFIG_SPI_FLASH_ATMEL
  93 #define CONFIG_SPI_FLASH_SPANSION
  94 #define CONFIG_SPI_FLASH_STMICRO
  95 #define CONFIG_SPI_FLASH_WINBOND
  96
  97
  98 /*
  99  * Env Storage Settings
 100  */
 101 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
 102 #define CONFIG_ENV_IS_IN_SPI_FLASH
 103 #define CONFIG_ENV_OFFSET       0x10000
 104 #define CONFIG_ENV_SIZE         0x2000
 105 #define CONFIG_ENV_SECT_SIZE    0x10000
 106 #else
 107 #define CONFIG_ENV_IS_IN_FLASH
 108 #define CONFIG_ENV_OFFSET       0x4000
 109 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 110 #define CONFIG_ENV_SIZE         0x2000
 111 #define CONFIG_ENV_SECT_SIZE    0x2000
 112 #endif
 113 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
 114 #define ENV_IS_EMBEDDED
 115 #else
 116 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 117 #endif
 118 #ifdef ENV_IS_EMBEDDED
 119 /* WARNING - the following is hand-optimized to fit within
 120  * the sector before the environment sector. If it throws
 121  * an error during compilation remove an object here to get
 122  * it linked after the configuration sector.
 123  */
 124 # define LDS_BOARD_TEXT \
 125         arch/blackfin/cpu/traps.o               (.text .text.*); \
 126         arch/blackfin/cpu/interrupt.o   (.text .text.*); \
 127         arch/blackfin/cpu/serial.o              (.text .text.*); \
 128         common/dlmalloc.o               (.text .text.*); \
 129         lib/crc32.o             (.text .text.*); \
 130         . = DEFINED(env_offset) ? env_offset : .; \
 131         common/env_embedded.o           (.text .text.*);
 132 #endif
 133
 134
 135 /*
 136  * I2C Settings
 137  */
 138 #define CONFIG_BFIN_TWI_I2C     1
 139 #define CONFIG_HARD_I2C         1
 140
 141
 142 /*
 143  * SPI_MMC Settings
 144  */
 145 #define CONFIG_MMC
 146 #define CONFIG_SPI_MMC
 147
 148
 149 /*
 150  * NAND Settings
 151  */
 152 /* #define CONFIG_NAND_PLAT */
 153 #define CONFIG_SYS_NAND_BASE            0x20212000
 154 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 155
 156 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 157 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
 158 #define BFIN_NAND_WRITE(addr, cmd) \
 159         do { \
 160                 bfin_write8(addr, cmd); \
 161                 SSYNC(); \
 162         } while (0)
 163
 164 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 165 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
 166 #define NAND_PLAT_GPIO_DEV_READY       GPIO_PF3
 167
 168
 169 /*
 170  * CF-CARD IDE-HDD Support
 171  */
 172
 173 /*
 174  * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card)
 175  * Strange address mapping Blackfin A13 connects to CF_A0
 176  */
 177
 178 /* #define CONFIG_BFIN_TRUE_IDE */
 179
 180 /*
 181  * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card)
 182  * This should be the preferred mode
 183  */
 184
 185 /* #define CONFIG_BFIN_CF_IDE */
 186
 187 /*
 188  * Add IDE Disk Drive (HDD) support
 189  * See example interface here:
 190  * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin
 191  */
 192
 193 /* #define CONFIG_BFIN_HDD_IDE */
 194
 195 #if defined(CONFIG_BFIN_CF_IDE) || \
 196     defined(CONFIG_BFIN_HDD_IDE) || \
 197     defined(CONFIG_BFIN_TRUE_IDE)
 198 # define CONFIG_BFIN_IDE        1
 199 # define CONFIG_CMD_IDE
 200 #endif
 201
 202 #if defined(CONFIG_BFIN_IDE)
 203
 204 #define CONFIG_DOS_PARTITION    1
 205 /*
 206  * IDE/ATA stuff
 207  */
 208 #undef  CONFIG_IDE_8xx_DIRECT   /* no pcmcia interface required */
 209 #undef  CONFIG_IDE_LED          /* no led for ide supported */
 210 #undef  CONFIG_IDE_RESET        /* no reset for ide supported */
 211
 212 #define CONFIG_SYS_IDE_MAXBUS           1
 213 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS * 1)
 214
 215 #undef  CONFIG_EBIU_AMBCTL1_VAL
 216 #define CONFIG_EBIU_AMBCTL1_VAL         0xFFC3FFC3
 217
 218 #define CONFIG_CF_ATASEL_DIS    0x20311800
 219 #define CONFIG_CF_ATASEL_ENA    0x20311802
 220
 221 #if defined(CONFIG_BFIN_TRUE_IDE)
 222 /*
 223  * Note that these settings aren't for the most part used in include/ata.h
 224  * when all of the ATA registers are setup
 225  */
 226 #define CONFIG_SYS_ATA_BASE_ADDR        0x2031C000
 227 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 228 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0020  /* data I/O */
 229 #define CONFIG_SYS_ATA_REG_OFFSET       0x0020  /* normal register accesses */
 230 #define CONFIG_SYS_ATA_ALT_OFFSET       0x001C  /* alternate registers */
 231 #define CONFIG_SYS_ATA_STRIDE           2       /* CF.A0 --> Blackfin.A13 */
 232
 233 #elif defined(CONFIG_BFIN_CF_IDE)
 234 #define CONFIG_SYS_ATA_BASE_ADDR        0x20211800
 235 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 236 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* data I/O */
 237 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* normal register accesses */
 238 #define CONFIG_SYS_ATA_ALT_OFFSET       0x000E  /* alternate registers */
 239 #define CONFIG_SYS_ATA_STRIDE           1       /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */
 240
 241 #elif defined(CONFIG_BFIN_HDD_IDE)
 242 #define CONFIG_SYS_ATA_BASE_ADDR        0x20314000
 243 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 244 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0020  /* data I/O */
 245 #define CONFIG_SYS_ATA_REG_OFFSET       0x0020  /* normal register accesses */
 246 #define CONFIG_SYS_ATA_ALT_OFFSET       0x001C  /* alternate registers */
 247 #define CONFIG_SYS_ATA_STRIDE           2       /* CF.A0 --> Blackfin.A1 */
 248 #undef  CONFIG_SCLK_DIV
 249 #define CONFIG_SCLK_DIV         8
 250 #endif
 251
 252 #endif
 253
 254
 255 /*
 256  * Misc Settings
 257  */
 258 #define CONFIG_MISC_INIT_R
 259 #define CONFIG_RTC_BFIN
 260 #define CONFIG_UART_CONSOLE     0
 261
 262 /* Define if want to do post memory test */
 263 #undef CONFIG_POST
 264 #ifdef CONFIG_POST
 265 #define FLASH_START_POST_BLOCK  11      /* Should > = 11 */
 266 #define FLASH_END_POST_BLOCK    71      /* Should < = 71 */
 267 #endif
 268
 269 /* These are for board tests */
 270 #if 0
 271 #define CONFIG_BOOTCOMMAND       "bootldr 0x203f0100"
 272 #define CONFIG_AUTOBOOT_KEYED
 273 #define CONFIG_AUTOBOOT_PROMPT \
 274         "autoboot in %d seconds: press space to stop\n", bootdelay
 275 #define CONFIG_AUTOBOOT_STOP_STR " "
 276 #endif
 277
 278
 279 /*
 280  * Pull in common ADI header for remaining command/environment setup
 281  */
 282 #include <configs/bfin_adi_common.h>
 283
 284 #endif