include/configs/bf537-stamp.h

   1 /*
   2  * U-Boot - Configuration file for BF537 STAMP board
   3  */
   4
   5 #ifndef __CONFIG_BF537_STAMP_H__
   6 #define __CONFIG_BF537_STAMP_H__
   7
   8 #include <asm/config-pre.h>
   9
  10
  11 /*
  12  * Processor Settings
  13  */
  14 #define CONFIG_BFIN_CPU             bf537-0.2
  15 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
  16
  17
  18 /*
  19  * Clock Settings
  20  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
  21  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  22  */
  23 /* CONFIG_CLKIN_HZ is any value in Hz                                   */
  24 #define CONFIG_CLKIN_HZ                 25000000
  25 /* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
  26 /*                                                1 = CLKIN / 2         */
  27 #define CONFIG_CLKIN_HALF               0
  28 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
  29 /*                                                1 = bypass PLL        */
  30 #define CONFIG_PLL_BYPASS               0
  31 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
  32 /* Values can range from 0-63 (where 0 means 64)                        */
  33 #define CONFIG_VCO_MULT                 20
  34 /* CCLK_DIV controls the core clock divider                             */
  35 /* Values can be 1, 2, 4, or 8 ONLY                                     */
  36 #define CONFIG_CCLK_DIV                 1
  37 /* SCLK_DIV controls the system clock divider                           */
  38 /* Values can range from 1-15                                           */
  39 #define CONFIG_SCLK_DIV                 4
  40
  41
  42 /*
  43  * Memory Settings
  44  */
  45 #define CONFIG_MEM_ADD_WDTH     10
  46 #define CONFIG_MEM_SIZE         64
  47
  48 #define CONFIG_EBIU_SDRRC_VAL   0x306
  49 #define CONFIG_EBIU_SDGCTL_VAL  0x91114d
  50
  51 #define CONFIG_EBIU_AMGCTL_VAL  0xFF
  52 #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
  53 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
  54
  55 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  56 #define CONFIG_SYS_MALLOC_LEN           (384 * 1024)
  57
  58
  59 /*
  60  * Network Settings
  61  */
  62 #ifndef __ADSPBF534__
  63 #define ADI_CMDS_NETWORK        1
  64 #define CONFIG_BFIN_MAC
  65 #define CONFIG_NETCONSOLE       1
  66 #endif
  67 #define CONFIG_HOSTNAME         bf537-stamp
  68
  69 /*
  70  * Flash Settings
  71  */
  72 #define CONFIG_FLASH_CFI_DRIVER
  73 #define CONFIG_SYS_FLASH_BASE           0x20000000
  74 #define CONFIG_SYS_FLASH_CFI
  75 #define CONFIG_SYS_FLASH_PROTECTION
  76 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  77 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
  78 #define CONFIG_SYS_MAX_FLASH_SECT       71
  79
  80
  81 /*
  82  * SPI Settings
  83  */
  84 #define CONFIG_BFIN_SPI
  85 #define CONFIG_ENV_SPI_MAX_HZ   30000000
  86 #define CONFIG_SF_DEFAULT_SPEED 30000000
  87 #define CONFIG_SPI_FLASH_ALL
  88
  89
  90 /*
  91  * Env Storage Settings
  92  */
  93 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
  94 #define CONFIG_ENV_IS_IN_SPI_FLASH
  95 #define CONFIG_ENV_OFFSET       0x10000
  96 #define CONFIG_ENV_SIZE         0x2000
  97 #define CONFIG_ENV_SECT_SIZE    0x10000
  98 #else
  99 #define CONFIG_ENV_IS_IN_FLASH
 100 #define CONFIG_ENV_OFFSET       0x4000
 101 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 102 #define CONFIG_ENV_SIZE         0x2000
 103 #define CONFIG_ENV_SECT_SIZE    0x2000
 104 #endif
 105 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
 106 #define ENV_IS_EMBEDDED
 107 #else
 108 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 109 #endif
 110 #ifdef ENV_IS_EMBEDDED
 111 /* WARNING - the following is hand-optimized to fit within
 112  * the sector before the environment sector. If it throws
 113  * an error during compilation remove an object here to get
 114  * it linked after the configuration sector.
 115  */
 116 # define LDS_BOARD_TEXT \
 117         arch/blackfin/lib/built-in.o (.text*); \
 118         arch/blackfin/cpu/built-in.o (.text*); \
 119         . = DEFINED(env_offset) ? env_offset : .; \
 120         common/env_embedded.o (.text*);
 121 #endif
 122
 123
 124 /*
 125  * I2C Settings
 126  */
 127 #define CONFIG_SYS_I2C
 128 #define CONFIG_SYS_I2C_ADI
 129
 130
 131 /*
 132  * SPI_MMC Settings
 133  */
 134 #define CONFIG_MMC_SPI
 135 #ifdef CONFIG_MMC_SPI
 136 #define CONFIG_MMC
 137 #define CONFIG_GENERIC_MMC
 138 #endif
 139
 140 /*
 141  * NAND Settings
 142  */
 143 /* #define CONFIG_NAND_PLAT */
 144 #ifdef CONFIG_NAND_PLAT
 145 #define CONFIG_SYS_NAND_BASE            0x20212000
 146 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 147
 148 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 149 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
 150 #define BFIN_NAND_WRITE(addr, cmd) \
 151         do { \
 152                 bfin_write8(addr, cmd); \
 153                 SSYNC(); \
 154         } while (0)
 155
 156 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 157 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
 158 #define NAND_PLAT_GPIO_DEV_READY       GPIO_PF3
 159 #endif /* CONFIG_NAND_PLAT */
 160
 161 /*
 162  * CF-CARD IDE-HDD Support
 163  */
 164
 165 /*
 166  * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card)
 167  * Strange address mapping Blackfin A13 connects to CF_A0
 168  */
 169
 170 /* #define CONFIG_BFIN_TRUE_IDE */
 171
 172 /*
 173  * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card)
 174  * This should be the preferred mode
 175  */
 176
 177 /* #define CONFIG_BFIN_CF_IDE */
 178
 179 /*
 180  * Add IDE Disk Drive (HDD) support
 181  * See example interface here:
 182  * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin
 183  */
 184
 185 /* #define CONFIG_BFIN_HDD_IDE */
 186
 187 #if defined(CONFIG_BFIN_CF_IDE) || \
 188     defined(CONFIG_BFIN_HDD_IDE) || \
 189     defined(CONFIG_BFIN_TRUE_IDE)
 190 # define CONFIG_BFIN_IDE        1
 191 # define CONFIG_CMD_IDE
 192 #endif
 193
 194 #if defined(CONFIG_BFIN_IDE)
 195
 196 #define CONFIG_DOS_PARTITION    1
 197 /*
 198  * IDE/ATA stuff
 199  */
 200 #undef  CONFIG_IDE_8xx_DIRECT   /* no pcmcia interface required */
 201 #undef  CONFIG_IDE_LED          /* no led for ide supported */
 202 #undef  CONFIG_IDE_RESET        /* no reset for ide supported */
 203
 204 #define CONFIG_SYS_IDE_MAXBUS           1
 205 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS * 1)
 206
 207 #undef  CONFIG_EBIU_AMBCTL1_VAL
 208 #define CONFIG_EBIU_AMBCTL1_VAL         0xFFC3FFC3
 209
 210 #define CONFIG_CF_ATASEL_DIS    0x20311800
 211 #define CONFIG_CF_ATASEL_ENA    0x20311802
 212
 213 #if defined(CONFIG_BFIN_TRUE_IDE)
 214 /*
 215  * Note that these settings aren't for the most part used in include/ata.h
 216  * when all of the ATA registers are setup
 217  */
 218 #define CONFIG_SYS_ATA_BASE_ADDR        0x2031C000
 219 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 220 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0020  /* data I/O */
 221 #define CONFIG_SYS_ATA_REG_OFFSET       0x0020  /* normal register accesses */
 222 #define CONFIG_SYS_ATA_ALT_OFFSET       0x001C  /* alternate registers */
 223 #define CONFIG_SYS_ATA_STRIDE           2       /* CF.A0 --> Blackfin.A13 */
 224
 225 #elif defined(CONFIG_BFIN_CF_IDE)
 226 #define CONFIG_SYS_ATA_BASE_ADDR        0x20211800
 227 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 228 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* data I/O */
 229 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* normal register accesses */
 230 #define CONFIG_SYS_ATA_ALT_OFFSET       0x000E  /* alternate registers */
 231 #define CONFIG_SYS_ATA_STRIDE           1       /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */
 232
 233 #elif defined(CONFIG_BFIN_HDD_IDE)
 234 #define CONFIG_SYS_ATA_BASE_ADDR        0x20314000
 235 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 236 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0020  /* data I/O */
 237 #define CONFIG_SYS_ATA_REG_OFFSET       0x0020  /* normal register accesses */
 238 #define CONFIG_SYS_ATA_ALT_OFFSET       0x001C  /* alternate registers */
 239 #define CONFIG_SYS_ATA_STRIDE           2       /* CF.A0 --> Blackfin.A1 */
 240 #undef  CONFIG_SCLK_DIV
 241 #define CONFIG_SCLK_DIV         8
 242 #endif
 243
 244 #endif
 245
 246
 247 /*
 248  * Misc Settings
 249  */
 250 #define CONFIG_MISC_INIT_R
 251 #define CONFIG_RTC_BFIN
 252 #define CONFIG_UART_CONSOLE     0
 253
 254 /* Define if want to do post memory test */
 255 #undef CONFIG_POST
 256 #ifdef CONFIG_POST
 257 #define CONFIG_SYS_POST_HOTKEYS_GPIO    GPIO_PF5
 258 #define CONFIG_POST_BSPEC1_GPIO_LEDS \
 259         GPIO_PF6, GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11,
 260 #define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
 261         GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2,
 262 #define CONFIG_POST_BSPEC2_GPIO_NAMES \
 263         10, 11, 12, 13,
 264 #define CONFIG_SYS_POST_FLASH_START     11
 265 #define CONFIG_SYS_POST_FLASH_END       71
 266 #endif
 267
 268 /* These are for board tests */
 269 #if 0
 270 #define CONFIG_BOOTCOMMAND       "bootldr 0x203f0100"
 271 #endif
 272
 273
 274 /*
 275  * Pull in common ADI header for remaining command/environment setup
 276  */
 277 #include <configs/bfin_adi_common.h>
 278
 279 #endif