include/configs/bf548-ezkit.h

   1 /*
   2  * U-Boot - Configuration file for BF548 STAMP board
   3  */
   4
   5 #ifndef __CONFIG_BF548_EZKIT_H__
   6 #define __CONFIG_BF548_EZKIT_H__
   7
   8 #include <asm/config-pre.h>
   9
  10
  11 /*
  12  * Processor Settings
  13  */
  14 #define CONFIG_BFIN_CPU             bf548-0.0
  15 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
  16
  17
  18 /*
  19  * Clock Settings
  20  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
  21  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  22  */
  23 /* CONFIG_CLKIN_HZ is any value in Hz                                   */
  24 #define CONFIG_CLKIN_HZ                 25000000
  25 /* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
  26 /*                                                1 = CLKIN / 2         */
  27 #define CONFIG_CLKIN_HALF               0
  28 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
  29 /*                                                1 = bypass PLL        */
  30 #define CONFIG_PLL_BYPASS               0
  31 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
  32 /* Values can range from 0-63 (where 0 means 64)                        */
  33 #define CONFIG_VCO_MULT                 21
  34 /* CCLK_DIV controls the core clock divider                             */
  35 /* Values can be 1, 2, 4, or 8 ONLY                                     */
  36 #define CONFIG_CCLK_DIV                 1
  37 /* SCLK_DIV controls the system clock divider                           */
  38 /* Values can range from 1-15                                           */
  39 #define CONFIG_SCLK_DIV                 4
  40
  41
  42 /*
  43  * Memory Settings
  44  */
  45 #define CONFIG_MEM_ADD_WDTH     10
  46 #define CONFIG_MEM_SIZE         64
  47
  48 #define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE
  49 #define CONFIG_EBIU_DDRCTL1_VAL 0x20022222
  50 #define CONFIG_EBIU_DDRCTL2_VAL 0x00000021
  51
  52 /* Default EZ-Kit bank mapping:
  53  *      Async Bank 0 - 32MB Burst Flash
  54  *      Async Bank 1 - Ethernet
  55  *      Async Bank 2 - Nothing
  56  *      Async Bank 3 - Nothing
  57  */
  58 #define CONFIG_EBIU_AMGCTL_VAL  0xFF
  59 #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
  60 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
  61 #define CONFIG_EBIU_FCTL_VAL    (BCLK_4)
  62 #define CONFIG_EBIU_MODE_VAL    (B0MODE_FLASH)
  63
  64 #define CONFIG_SYS_MONITOR_LEN  (1024 * 1024)
  65 #define CONFIG_SYS_MALLOC_LEN   (768 * 1024)
  66
  67
  68 /*
  69  * Network Settings
  70  */
  71 #define ADI_CMDS_NETWORK        1
  72 #define CONFIG_SMC911X  1
  73 #define CONFIG_SMC911X_BASE     0x24000000
  74 #define CONFIG_SMC911X_16_BIT
  75 #define CONFIG_HOSTNAME         bf548-ezkit
  76
  77
  78 /*
  79  * Flash Settings
  80  */
  81 #define CONFIG_FLASH_CFI_DRIVER
  82 #define CONFIG_SYS_FLASH_BASE           0x20000000
  83 #define CONFIG_SYS_FLASH_CFI
  84 #define CONFIG_SYS_FLASH_PROTECTION
  85 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  86 #define CONFIG_SYS_MAX_FLASH_SECT       259
  87
  88
  89 /*
  90  * SPI Settings
  91  */
  92 #define CONFIG_BFIN_SPI
  93 #define CONFIG_ENV_SPI_MAX_HZ   30000000
  94 #define CONFIG_SF_DEFAULT_SPEED 30000000
  95
  96
  97 /*
  98  * Env Storage Settings
  99  */
 100 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
 101 #define CONFIG_ENV_IS_IN_SPI_FLASH
 102 #define CONFIG_ENV_OFFSET       0x10000
 103 #define CONFIG_ENV_SIZE         0x2000
 104 #define CONFIG_ENV_SECT_SIZE    0x10000
 105 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 106 #elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
 107 #define CONFIG_ENV_IS_IN_NAND
 108 #define CONFIG_ENV_OFFSET       0x60000
 109 #define CONFIG_ENV_SIZE         0x20000
 110 #else
 111 /* The BF548-EZKIT uses a top boot flash */
 112 #define CONFIG_ENV_IS_IN_FLASH  1
 113 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 114 #define CONFIG_ENV_OFFSET       (0x1000000 - CONFIG_ENV_SECT_SIZE)
 115 #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 116 #define CONFIG_ENV_SECT_SIZE    0x8000
 117 #endif
 118
 119 /*
 120  * NAND Settings
 121  */
 122 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
 123 #define CONFIG_BFIN_NFC_CTL_VAL        0x0033
 124 #define CONFIG_BFIN_NFC_BOOTROM_ECC
 125 #define CONFIG_DRIVER_NAND_BFIN
 126 #define CONFIG_SYS_NAND_BASE           0 /* not actually used */
 127 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 128 #endif
 129
 130 /*
 131  * I2C Settings
 132  */
 133 #define CONFIG_SYS_I2C
 134 #define CONFIG_SYS_I2C_ADI
 135
 136
 137 /*
 138  * SATA
 139  */
 140 #if !defined(__ADSPBF544__)
 141 #define CONFIG_LIBATA
 142 #define CONFIG_SYS_SATA_MAX_DEVICE 1
 143 #define CONFIG_LBA48
 144 #define CONFIG_PATA_BFIN
 145 #define CONFIG_BFIN_ATAPI_BASE_ADDR     0xFFC03800
 146 #define CONFIG_BFIN_ATA_MODE    XFER_PIO_4
 147 #endif
 148
 149
 150 /*
 151  * SDH Settings
 152  */
 153 #if !defined(__ADSPBF544__)
 154 #define CONFIG_GENERIC_MMC
 155 #define CONFIG_MMC
 156 #define CONFIG_BFIN_SDH
 157 #endif
 158
 159
 160 /*
 161  * USB Settings
 162  */
 163 #if !defined(__ADSPBF544__)
 164 #define CONFIG_USB
 165 #define CONFIG_USB_MUSB_HCD
 166 #define CONFIG_USB_BLACKFIN
 167 #define CONFIG_USB_STORAGE
 168 #define CONFIG_USB_MUSB_TIMEOUT 100000
 169 #endif
 170
 171
 172 /*
 173  * Misc Settings
 174  */
 175 #define CONFIG_BOARD_EARLY_INIT_F
 176 #define CONFIG_BOARD_SIZE_LIMIT $$(( 512 * 1024 ))
 177 #define CONFIG_RTC_BFIN
 178 #define CONFIG_UART_CONSOLE     1
 179 #define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
 180
 181 #define CONFIG_ADI_GPIO2
 182
 183 #undef CONFIG_VIDEO
 184 #ifdef CONFIG_VIDEO
 185 #define EASYLOGO_HEADER < asm/bfin_logo_230x230_gzip.h >
 186 #define CONFIG_DEB_DMA_URGENT
 187 #endif
 188
 189 /* Define if want to do post memory test */
 190 #undef CONFIG_POST
 191 #ifdef CONFIG_POST
 192 #define CONFIG_POST_BSPEC1_GPIO_LEDS \
 193         GPIO_PG6, GPIO_PG7, GPIO_PG8, GPIO_PG9, GPIO_PG10, GPIO_PG11,
 194 #define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
 195         GPIO_PB8, GPIO_PB9, GPIO_PB10, GPIO_PB11
 196 #define CONFIG_POST_BSPEC2_GPIO_NAMES \
 197         13, 12, 11, 10,
 198 #define CONFIG_SYS_POST_FLASH_START     10
 199 #define CONFIG_SYS_POST_FLASH_END       127
 200 #endif
 201
 202
 203 /*
 204  * Pull in common ADI header for remaining command/environment setup
 205  */
 206 #include <configs/bfin_adi_common.h>
 207
 208 #endif