include/configs/bf561-acvilon.h

   1 /*
   2  * U-Boot - Configuration file for BF561 Acvilon System On Module
   3  * For more information please go to http://www.niistt.ru/
   4  */
   5
   6 #ifndef __CONFIG_BF561_ACVILON_H__
   7 #define __CONFIG_BF561_ACVILON_H__
   8
   9 #include <asm/config-pre.h>
  10
  11 /*
  12  * Processor Settings
  13  */
  14 #define CONFIG_BFIN_CPU             bf561-0.5
  15 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
  16
  17 /*
  18  * Clock Settings
  19  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
  20  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  21  */
  22 /* CONFIG_CLKIN_HZ is any value in Hz                                   */
  23 #define CONFIG_CLKIN_HZ                         12000000
  24 /* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
  25 /*                                                1 = CLKIN / 2         */
  26 #define CONFIG_CLKIN_HALF                       0
  27 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
  28 /*                                                1 = bypass PLL        */
  29 #define CONFIG_PLL_BYPASS                       0
  30 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
  31 /* Values can range from 0-63 (where 0 means 64)                        */
  32 #define CONFIG_VCO_MULT                         50
  33 /* CCLK_DIV controls the core clock divider                             */
  34 /* Values can be 1, 2, 4, or 8 ONLY                                     */
  35 #define CONFIG_CCLK_DIV                         1
  36 /* SCLK_DIV controls the system clock divider                           */
  37 /* Values can range from 1-15                                           */
  38 #define CONFIG_SCLK_DIV                         5
  39
  40 /*
  41  * Memory Settings
  42  */
  43 #define CONFIG_MEM_ADD_WDTH                     10
  44 #define CONFIG_MEM_SIZE                         128
  45
  46 #define CONFIG_EBIU_SDRRC_VAL           0x300
  47 #define CONFIG_EBIU_SDGCTL_VAL          0x00B11189
  48
  49 #define CONFIG_EBIU_AMGCTL_VAL          0x4e
  50 #define CONFIG_EBIU_AMBCTL0_VAL         0xffc2ffc2
  51 #define CONFIG_EBIU_AMBCTL1_VAL         0x99b35554
  52
  53 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)
  54 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
  55
  56 /*
  57  * RTC Settings
  58  */
  59 #define CONFIG_RTC_DS1337
  60 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  61
  62 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
  63 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
  64 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
  65 #define CONFIG_SYS_I2C_DTT_ADDR 0x49
  66 /*#define CONFIG_SYS_DTT_MAX_TEMP 70
  67 #define CONFIG_SYS_DTT_LOW_TEMP -30
  68 #define CONFIG_SYS_DTT_HYSTERESIS       3*/
  69
  70 /*
  71  * Network Settings
  72  */
  73 #define ADI_CMDS_NETWORK                        1
  74 #define CONFIG_CMD_DATE
  75 #define CONFIG_CMD_DTT
  76
  77 #if defined(CONFIG_CMD_NET)
  78
  79 #define CONFIG_SMC911X                          1
  80 #define CONFIG_SMC911X_32_BIT
  81 /* #define CONFIG_SMC911X_16_BIT */
  82 #define CONFIG_SMC911X_BASE                     0x28000000
  83
  84 #endif /* (CONFIG_CMD_NET) */
  85
  86 #define CONFIG_HOSTNAME         bf561-acvilon
  87
  88 /*
  89  * I2C Settings
  90  */
  91 #define CONFIG_HARD_I2C
  92 /* Use 300kHz speed by default */
  93 #define CONFIG_SYS_I2C_SPEED                    0x00
  94 #define CONFIG_PCA9564_I2C
  95 #define CONFIG_PCA9564_BASE                     0x2c000000
  96
  97 /*
  98  * SPI Settings
  99  */
 100 #define CONFIG_BFIN_SPI
 101 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 102 #define CONFIG_SF_DEFAULT_SPEED         10000000
 103
 104 /*
 105  * Env Storage Settings
 106  */
 107 #define CONFIG_ENV_IS_IN_SPI_FLASH
 108 #define CONFIG_ENV_SECT_SIZE            (1056 * 8)
 109 #define CONFIG_ENV_OFFSET                       ((16 + 256) * 1056)
 110 #define CONFIG_ENV_SIZE                         (8 * 1056)
 111
 112 /*
 113  * NAND Settings
 114  * We're using NAND_PLAT driver to make things simplier
 115  */
 116 #define CONFIG_NAND_PLAT
 117 #define CONFIG_CMD_NAND
 118 #define CONFIG_SYS_NAND_BASE            0x24000000
 119 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 120
 121 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 122 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3))
 123 #define BFIN_NAND_WRITE(addr, cmd) \
 124         do { \
 125                 bfin_write8(addr, cmd); \
 126                 SSYNC(); \
 127         } while (0)
 128
 129 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 130 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
 131 #define NAND_PLAT_GPIO_DEV_READY       GPIO_PF10
 132
 133 /*
 134  * Misc Settings
 135  */
 136 #define CONFIG_UART_CONSOLE                     0
 137
 138 /*
 139  * Pull in common ADI header for remaining command/environment setup
 140  */
 141 #include <configs/bfin_adi_common.h>
 142
 143 #endif                          /* __CONFIG_BF561_ACVILON_H__ */