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Move defaults from config_cmd_default.h to Kconfig
[people/ms/u-boot.git] / include / configs / blackstamp.h
1 /*
2 * U-boot - Configuration file for BlackStamp board
3 * Configuration by Ben Matthews for UR LLE using bf533-stamp.h
4 * as a template
5 * See http://blackfin.uclinux.org/gf/project/blackstamp/
6 */
7
8 #ifndef __CONFIG_BLACKSTAMP_H__
9 #define __CONFIG_BLACKSTAMP_H__
10
11 #include <asm/config-pre.h>
12
13 /*
14 * Debugging: Set these options if you're having problems
15 */
16 /*
17 * #define CONFIG_DEBUG_EARLY_SERIAL
18 * #define DEBUG
19 * #define CONFIG_DEBUG_DUMP
20 * #define CONFIG_DEBUG_DUMP_SYMS
21 */
22 #define CONFIG_PANIC_HANG 0
23
24 /* CPU Options
25 * Be sure to set the Silicon Revision Correctly
26 */
27 #define CONFIG_BFIN_CPU bf532-0.5
28 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
29
30 /*
31 * Board settings
32 */
33 #define CONFIG_SMC91111 1
34 #define CONFIG_SMC91111_BASE 0x20300300
35
36 /* FLASH/ETHERNET uses the same address range
37 * Depending on what you have the CPLD doing
38 * this probably isn't needed
39 */
40 #define SHARED_RESOURCES 1
41
42 /* Is I2C bit-banged? */
43
44 /*
45 * Clock Settings
46 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
47 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
48 */
49 /* CONFIG_CLKIN_HZ is any value in Hz */
50 #define CONFIG_CLKIN_HZ 25000000
51 /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
52 /* 1 = CLKIN / 2 */
53 #define CONFIG_CLKIN_HALF 0
54 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
55 /* 1 = bypass PLL */
56 #define CONFIG_PLL_BYPASS 0
57 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
58 /* Values can range from 0-63 (where 0 means 64) */
59 #define CONFIG_VCO_MULT 16
60 /* CCLK_DIV controls the core clock divider */
61 /* Values can be 1, 2, 4, or 8 ONLY */
62 #define CONFIG_CCLK_DIV 1
63 /* SCLK_DIV controls the system clock divider */
64 /* Values can range from 1-15 */
65 #define CONFIG_SCLK_DIV 3
66
67 /*
68 * Network settings
69 */
70
71 #ifdef CONFIG_SMC91111
72 #define CONFIG_IPADDR 192.168.0.15
73 #define CONFIG_NETMASK 255.255.255.0
74 #define CONFIG_GATEWAYIP 192.168.0.1
75 #define CONFIG_SERVERIP 192.168.0.2
76 #define CONFIG_HOSTNAME blackstamp
77 #define CONFIG_ROOTPATH "/checkout/uClinux-dist/romfs"
78 #define CONFIG_SYS_AUTOLOAD "no"
79 #endif
80
81 #define CONFIG_ENV_IS_IN_SPI_FLASH
82 #define CONFIG_ENV_OFFSET 0x40000
83 #define CONFIG_ENV_SIZE 0x2000
84 #define CONFIG_ENV_SECT_SIZE 0x40000
85
86 /*
87 * SDRAM settings & memory map
88 */
89
90 #define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
91 #define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */
92
93 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
94 #define CONFIG_SYS_MALLOC_LEN (384 << 10)
95
96 /*
97 * Command settings
98 */
99
100 #define CONFIG_SYS_LONGHELP 1
101 #define CONFIG_CMDLINE_EDITING 1
102 #define CONFIG_AUTO_COMPLETE 1
103 #define CONFIG_ENV_OVERWRITE 1
104
105 #ifdef CONFIG_SMC91111
106 # define CONFIG_CMD_DHCP
107 # define CONFIG_CMD_PING
108 #else
109 #endif
110
111 #ifdef CONFIG_SYS_I2C_SOFT
112 # define CONFIG_CMD_I2C
113 #endif
114
115 #define CONFIG_CMD_BOOTLDR
116 #define CONFIG_CMD_CACHE
117 #define CONFIG_CMD_CPLBINFO
118 #define CONFIG_CMD_DATE
119 #define CONFIG_CMD_SF
120 #define CONFIG_CMD_ELF
121
122 #define CONFIG_BOOTDELAY 5
123 #define CONFIG_BOOTCOMMAND "run ramboot"
124 #define CONFIG_BOOTARGS \
125 "root=/dev/mtdblock0 rw " \
126 "clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
127 "earlyprintk=" \
128 "serial," \
129 "uart" __stringify(CONFIG_UART_CONSOLE) "," \
130 __stringify(CONFIG_BAUDRATE) " " \
131 "console=ttyBF0," __stringify(CONFIG_BAUDRATE)
132
133 #if defined(CONFIG_CMD_NET)
134 # if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
135 # define UBOOT_ENV_FILE "u-boot.bin"
136 # else
137 # define UBOOT_ENV_FILE "u-boot.ldr"
138 # endif
139 # if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
140 # ifdef CONFIG_SPI
141 # define UBOOT_ENV_UPDATE \
142 "eeprom write $(loadaddr) 0x0 $(filesize)"
143 # else
144 # define UBOOT_ENV_UPDATE \
145 "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
146 "sf erase 0 0x40000;" \
147 "sf write $(loadaddr) 0 $(filesize)"
148 # endif
149 # else
150 # define UBOOT_ENV_UPDATE \
151 "protect off 0x20000000 0x2003FFFF;" \
152 "erase 0x20000000 0x2003FFFF;" \
153 "cp.b $(loadaddr) 0x20000000 $(filesize)"
154 # endif
155 # define NETWORK_ENV_SETTINGS \
156 "ubootfile=" UBOOT_ENV_FILE "\0" \
157 "update=" \
158 "tftp $(loadaddr) $(ubootfile);" \
159 UBOOT_ENV_UPDATE \
160 "\0" \
161 "addip=set bootargs $(bootargs) " \
162 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \
163 "$(hostname):eth0:off" \
164 "\0" \
165 "ramargs=set bootargs " CONFIG_BOOTARGS "\0" \
166 "ramboot=" \
167 "tftp $(loadaddr) uImage;" \
168 "run ramargs;" \
169 "run addip;" \
170 "bootm" \
171 "\0" \
172 "nfsargs=set bootargs " \
173 "root=/dev/nfs rw " \
174 "nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \
175 "\0" \
176 "nfsboot=" \
177 "tftp $(loadaddr) vmImage;" \
178 "run nfsargs;" \
179 "run addip;" \
180 "bootm" \
181 "\0"
182 #else
183 # define NETWORK_ENV_SETTINGS
184 #endif
185
186 /*
187 * Console settings
188 */
189 #define CONFIG_BAUDRATE 57600
190 #define CONFIG_LOADS_ECHO 1
191 #define CONFIG_UART_CONSOLE 0
192 #define CONFIG_BFIN_SERIAL
193
194 /*
195 * I2C settings
196 * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
197 * Located on the expansion connector on pins 86/85
198 * Note these pins are arbitrarily chosen because we aren't using
199 * them yet. You can (and probably should) change these values!
200 */
201 #ifdef CONFIG_SYS_I2C_SOFT
202 #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF9
203 #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF8
204 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
205 #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
206 #endif
207
208 /*
209 * Miscellaneous configurable options
210 */
211 #define CONFIG_RTC_BFIN 1
212
213 /*
214 * Serial Flash Infomation
215 */
216 #define CONFIG_BFIN_SPI
217 /* For the M25P64 SCK Should be Kept < 15Mhz */
218 #define CONFIG_ENV_SPI_MAX_HZ 15000000
219 #define CONFIG_SF_DEFAULT_SPEED 15000000
220 #define CONFIG_SPI_FLASH_STMICRO
221
222 /*
223 * FLASH organization and environment definitions
224 */
225
226 #define CONFIG_EBIU_AMGCTL_VAL 0xFF
227 #define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
228 #define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
229 #define CONFIG_EBIU_SDRRC_VAL 0x268
230 #define CONFIG_EBIU_SDGCTL_VAL 0x911109
231
232 /* Even though Rev C boards have Parallel Flash
233 * We aren't supporting it. Newer versions of the
234 * hardware don't support Parallel Flash at all.
235 */
236 #define CONFIG_SYS_NO_FLASH
237 #undef CONFIG_CMD_JFFS2
238
239 #endif