include/configs/bubinga.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  21 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  22 #define CONFIG_BUBINGA          1       /* ...on a BUBINGA board        */
  23
  24 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  25
  26 /*
  27  * Include common defines/options for all AMCC eval boards
  28  */
  29 #define CONFIG_HOSTNAME         bubinga
  30 #include "amcc-common.h"
  31
  32 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  33
  34 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  35
  36 #define CONFIG_NO_SERIAL_EEPROM
  37 /*#undef CONFIG_NO_SERIAL_EEPROM*/
  38 /*----------------------------------------------------------------------------*/
  39 #ifdef CONFIG_NO_SERIAL_EEPROM
  40
  41 /*
  42 !-------------------------------------------------------------------------------
  43 ! Defines for entry options.
  44 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
  45 !       are plugged in the board will be utilized as non-ECC DIMMs.
  46 !-------------------------------------------------------------------------------
  47 */
  48 #define        AUTO_MEMORY_CONFIG
  49 #define        DIMM_READ_ADDR 0xAB
  50 #define        DIMM_WRITE_ADDR 0xAA
  51
  52 /*
  53 !-------------------------------------------------------------------------------
  54 ! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
  55 ! assuming a 33MHz input clock to the 405EP from the C9531.
  56 !-------------------------------------------------------------------------------
  57 */
  58 #define PLLMR0_DEFAULT   PLLMR0_266_133_66
  59 #define PLLMR1_DEFAULT   PLLMR1_266_133_66
  60
  61 #endif
  62 /*----------------------------------------------------------------------------*/
  63
  64 /*
  65  * Define here the location of the environment variables (FLASH or NVRAM).
  66  * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
  67  *       supported for backward compatibility.
  68  */
  69 #if 1
  70 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
  71 #else
  72 #define CONFIG_ENV_IS_IN_NVRAM  1       /* use NVRAM for environment vars       */
  73 #endif
  74
  75 /*
  76  * Default environment variables
  77  */
  78 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  79         CONFIG_AMCC_DEF_ENV                                             \
  80         CONFIG_AMCC_DEF_ENV_PPC                                         \
  81         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
  82         "kernel_addr=fff80000\0"                                        \
  83         "ramdisk_addr=fff90000\0"                                       \
  84         ""
  85
  86 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
  87 #define CONFIG_HAS_ETH0
  88 #define CONFIG_HAS_ETH1
  89 #define CONFIG_PHY1_ADDR        2       /* EMAC1 PHY address            */
  90
  91 #define CONFIG_RTC_DS174x       1       /* use DS1743 RTC in Bubinga    */
  92
  93 /*
  94  * Commands additional to the ones defined in amcc-common.h
  95  */
  96 #define CONFIG_CMD_DATE
  97 #define CONFIG_CMD_PCI
  98 #define CONFIG_CMD_SDRAM
  99 #define CONFIG_CMD_SNTP
 100
 101 #define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
 102
 103 /*
 104  * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 105  * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
 106  * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
 107  * The Linux BASE_BAUD define should match this configuration.
 108  *    baseBaud = cpuClock/(uartDivisor*16)
 109  * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
 110  * set Linux BASE_BAUD to 403200.
 111  */
 112 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 113 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
 114 #undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
 115 #define CONFIG_SYS_BASE_BAUD       691200
 116
 117 /*-----------------------------------------------------------------------
 118  * I2C stuff
 119  *-----------------------------------------------------------------------
 120  */
 121 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 122
 123 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }   /* avoid i2c probe hangup (?) */
 124 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   6       /* 24C02 requires 5ms delay */
 125
 126 #if defined(CONFIG_CMD_EEPROM)
 127 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* I2C boot EEPROM (24C02W)     */
 128 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1       /* Bytes of address             */
 129 #endif
 130
 131 /*-----------------------------------------------------------------------
 132  * PCI stuff
 133  *-----------------------------------------------------------------------
 134  */
 135 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 136 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 137 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 138
 139 #define CONFIG_PCI                      /* include pci support          */
 140 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 141 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 142 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 143                                         /* resource configuration       */
 144 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 145
 146 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC */
 147 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever */
 148 #define CONFIG_SYS_PCI_CLASSCODE       0x0600  /* PCI Class Code: bridge/host  */
 149 #define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
 150 #define CONFIG_SYS_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
 151 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 152 #define CONFIG_SYS_PCI_PTM2LA  0x00000000      /* disabled                     */
 153 #define CONFIG_SYS_PCI_PTM2MS  0x00000000      /* disabled                     */
 154 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 155
 156 /*-----------------------------------------------------------------------
 157  * External peripheral base address
 158  *-----------------------------------------------------------------------
 159  */
 160 #define CONFIG_SYS_KEY_REG_BASE_ADDR    0xF0100000
 161 #define CONFIG_SYS_IR_REG_BASE_ADDR     0xF0200000
 162 #define CONFIG_SYS_FPGA_REG_BASE_ADDR   0xF0300000
 163
 164 /*-----------------------------------------------------------------------
 165  * Start addresses for the final memory configuration
 166  * (Set up by the startup code)
 167  */
 168 #define CONFIG_SYS_SRAM_BASE            0xFFF00000
 169 #define CONFIG_SYS_SRAM_SIZE            (256 << 10)
 170 #define CONFIG_SYS_FLASH_BASE           0xFFF80000
 171
 172 /*-----------------------------------------------------------------------
 173  * FLASH organization
 174  */
 175 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 176 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 177
 178 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 179 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 180
 181 #define CONFIG_SYS_FLASH_ADDR0         0x5555
 182 #define CONFIG_SYS_FLASH_ADDR1         0x2aaa
 183 #define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char
 184
 185 #ifdef CONFIG_ENV_IS_IN_FLASH
 186 #define CONFIG_ENV_SECT_SIZE    0x10000 /* size of one complete sector  */
 187 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 188 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 189
 190 /* Address and size of Redundant Environment Sector     */
 191 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 192 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 193 #endif /* CONFIG_ENV_IS_IN_FLASH */
 194
 195 /*-----------------------------------------------------------------------
 196  * NVRAM organization
 197  */
 198 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xf0000000      /* NVRAM base address   */
 199 #define CONFIG_SYS_NVRAM_SIZE           0x1ff8          /* NVRAM size   */
 200
 201 #ifdef CONFIG_ENV_IS_IN_NVRAM
 202 #define CONFIG_ENV_SIZE         0x0ff8          /* Size of Environment vars     */
 203 #define CONFIG_ENV_ADDR         \
 204         (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)      /* Env  */
 205 #endif
 206
 207 /*
 208  * Init Memory Controller:
 209  *
 210  * BR0/1 and OR0/1 (FLASH)
 211  */
 212
 213 #define FLASH_BASE0_PRELIM      CONFIG_SYS_FLASH_BASE   /* FLASH bank #0        */
 214 #define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */
 215
 216 /*-----------------------------------------------------------------------
 217  * Definitions for initial stack pointer and data area (in data cache)
 218  */
 219 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 220 #define CONFIG_SYS_TEMP_STACK_OCM        1
 221
 222 /* On Chip Memory location */
 223 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 224 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 225 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 226 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 227
 228 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 229 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 230
 231 /*-----------------------------------------------------------------------
 232  * External Bus Controller (EBC) Setup
 233  */
 234
 235 /* Memory Bank 0 (Flash/SRAM) initialization                                    */
 236 #define CONFIG_SYS_EBC_PB0AP           0x04006000
 237 #define CONFIG_SYS_EBC_PB0CR           0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit  */
 238
 239 /* Memory Bank 1 (NVRAM/RTC) initialization                                     */
 240 #define CONFIG_SYS_EBC_PB1AP           0x04041000
 241 #define CONFIG_SYS_EBC_PB1CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 242
 243 /* Memory Bank 2 (not used) initialization                                      */
 244 #define CONFIG_SYS_EBC_PB2AP           0x00000000
 245 #define CONFIG_SYS_EBC_PB2CR           0x00000000
 246
 247 /* Memory Bank 2 (not used) initialization                                      */
 248 #define CONFIG_SYS_EBC_PB3AP           0x00000000
 249 #define CONFIG_SYS_EBC_PB3CR           0x00000000
 250
 251 /* Memory Bank 4 (FPGA regs) initialization                                     */
 252 #define CONFIG_SYS_EBC_PB4AP           0x01815000
 253 #define CONFIG_SYS_EBC_PB4CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
 254
 255 /*-----------------------------------------------------------------------
 256  * Definitions for Serial Presence Detect EEPROM address
 257  * (to get SDRAM settings)
 258  */
 259 #define SPD_EEPROM_ADDRESS      0x55
 260
 261 /*-----------------------------------------------------------------------
 262  * Definitions for GPIO setup (PPC405EP specific)
 263  *
 264  * GPIO0[0]     - External Bus Controller BLAST output
 265  * GPIO0[1-9]   - Instruction trace outputs
 266  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 267  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
 268  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 269  * GPIO0[24-27] - UART0 control signal inputs/outputs
 270  * GPIO0[28-29] - UART1 data signal input/output
 271  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 272  */
 273 #define CONFIG_SYS_GPIO0_OSRL          0x55555555
 274 #define CONFIG_SYS_GPIO0_OSRH          0x40000110
 275 #define CONFIG_SYS_GPIO0_ISR1L         0x00000000
 276 #define CONFIG_SYS_GPIO0_ISR1H         0x15555445
 277 #define CONFIG_SYS_GPIO0_TSRL          0x00000000
 278 #define CONFIG_SYS_GPIO0_TSRH          0x00000000
 279 #define CONFIG_SYS_GPIO0_TCR           0xFFFF8014
 280
 281 /*-----------------------------------------------------------------------
 282  * Some BUBINGA stuff...
 283  */
 284 #define NVRAM_BASE      0xF0000000
 285 #define FPGA_REG0       0xF0300000    /* FPGA Reg 0              */
 286 #define FPGA_REG1       0xF0300001    /* FPGA Reg 1              */
 287 #define NVRVFY1     0x4f532d4f    /* used to determine if state data in */
 288 #define NVRVFY2     0x50454e00    /* NVRAM initialized (ascii for OS-OPEN)*/
 289
 290 #define FPGA_REG0_F_RANGE     0x80       /* SDRAM PLL freq range              */
 291 #define FPGA_REG0_EXT_INT_DIS 0x20       /* External interface disable        */
 292 #define FPGA_REG0_LED_MASK    0x07       /* Board LEDs DS9, DS10, and DS11    */
 293 #define FPGA_REG0_LED0        0x04       /* Turn on LED0                      */
 294 #define FPGA_REG0_LED1        0x02       /* Turn on LED1                      */
 295 #define FPGA_REG0_LED2        0x01       /* Turn on LED2                      */
 296
 297 #define FPGA_REG1_SSPEC_DIS   0x80       /* C9531 Spread Spectrum disabled    */
 298 #define FPGA_REG1_OFFBD_PCICLK 0x40      /* Onboard PCI clock selected       */
 299 #define FPGA_REG1_CLOCK_MASK  0x30       /* Mask for C9531 output freq select */
 300 #define FPGA_REG1_CLOCK_BIT_SHIFT  4
 301 #define FPGA_REG1_PCI_INT_ARB 0x08       /* PCI Internal arbiter selected     */
 302 #define FPGA_REG1_PCI_FREQ    0x04       /* PCI Frequency select              */
 303 #define FPGA_REG1_OFFB_FLASH  0x02       /* Off board flash                   */
 304 #define FPGA_REG1_SRAM_BOOT   0x01       /* SRAM at 0xFFF80000 not Flash      */
 305
 306 #endif  /* __CONFIG_H */