include/configs/bubinga.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  37 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38 #define CONFIG_BUBINGA          1       /* ...on a BUBINGA board        */
  39
  40 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  41
  42 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  43
  44 #define CONFIG_NO_SERIAL_EEPROM
  45 /*#undef CONFIG_NO_SERIAL_EEPROM*/
  46 /*----------------------------------------------------------------------------*/
  47 #ifdef CONFIG_NO_SERIAL_EEPROM
  48
  49 /*
  50 !-------------------------------------------------------------------------------
  51 ! Defines for entry options.
  52 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
  53 !       are plugged in the board will be utilized as non-ECC DIMMs.
  54 !-------------------------------------------------------------------------------
  55 */
  56 #define        AUTO_MEMORY_CONFIG
  57 #define        DIMM_READ_ADDR 0xAB
  58 #define        DIMM_WRITE_ADDR 0xAA
  59
  60 /*
  61 !-------------------------------------------------------------------------------
  62 ! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
  63 ! assuming a 33MHz input clock to the 405EP from the C9531.
  64 !-------------------------------------------------------------------------------
  65 */
  66 #define PLLMR0_DEFAULT   PLLMR0_266_133_66
  67 #define PLLMR1_DEFAULT   PLLMR1_266_133_66
  68
  69 #endif
  70 /*----------------------------------------------------------------------------*/
  71
  72 /*
  73  * Define here the location of the environment variables (FLASH or NVRAM).
  74  * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
  75  *       supported for backward compatibility.
  76  */
  77 #if 1
  78 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars       */
  79 #else
  80 #define CFG_ENV_IS_IN_NVRAM     1       /* use NVRAM for environment vars       */
  81 #endif
  82
  83 #define CONFIG_PREBOOT  "echo;" \
  84         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  85         "echo"
  86
  87 #undef  CONFIG_BOOTARGS
  88
  89 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  90         "netdev=eth0\0"                                                 \
  91         "hostname=bubinga\0"                                            \
  92         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  93                 "nfsroot=${serverip}:${rootpath}\0"                     \
  94         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  95         "addip=setenv bootargs ${bootargs} "                            \
  96                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  97                 ":${hostname}:${netdev}:off panic=1\0"                  \
  98         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  99         "flash_nfs=run nfsargs addip addtty;"                           \
 100                 "bootm ${kernel_addr}\0"                                \
 101         "flash_self=run ramargs addip addtty;"                          \
 102                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 103         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 104                 "bootm\0"                                               \
 105         "rootpath=/opt/eldk/ppc_4xx\0"                                  \
 106         "bootfile=/tftpboot/bubinga/uImage\0"                           \
 107         "kernel_addr=fff80000\0"                                        \
 108         "ramdisk_addr=fff90000\0"                                       \
 109         "initrd_high=30000000\0"                                        \
 110         "load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0"               \
 111         "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"   \
 112                 "cp.b 100000 fffc0000 40000;"                           \
 113                 "setenv filesize;saveenv\0"                             \
 114         "upd=run load update\0"                                         \
 115         ""
 116 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 117
 118 #if 0
 119 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
 120 #else
 121 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 122 #endif
 123
 124 #define CONFIG_BAUDRATE         115200
 125
 126 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 127 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 128
 129 #define CONFIG_MII              1       /* MII PHY management           */
 130 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 131 #define CONFIG_HAS_ETH0
 132 #define CONFIG_HAS_ETH1
 133 #define CONFIG_PHY1_ADDR        2       /* EMAC1 PHY address            */
 134 #define CONFIG_NET_MULTI        1
 135 #define CFG_RX_ETH_BUFFER       16      /* Number of ethernet rx buffers & descriptors */
 136
 137 #define CONFIG_NETCONSOLE               /* include NetConsole support   */
 138
 139 #define CONFIG_RTC_DS174x       1       /* use DS1743 RTC in Bubinga    */
 140
 141
 142 /*
 143  * BOOTP options
 144  */
 145 #define CONFIG_BOOTP_BOOTFILESIZE
 146 #define CONFIG_BOOTP_BOOTPATH
 147 #define CONFIG_BOOTP_GATEWAY
 148 #define CONFIG_BOOTP_HOSTNAME
 149
 150
 151 /*
 152  * Command line configuration.
 153  */
 154 #include <config_cmd_default.h>
 155
 156 #define CONFIG_CMD_ASKENV
 157 #define CONFIG_CMD_CACHE
 158 #define CONFIG_CMD_DATE
 159 #define CONFIG_CMD_DHCP
 160 #define CONFIG_CMD_EEPROM
 161 #define CONFIG_CMD_ELF
 162 #define CONFIG_CMD_I2C
 163 #define CONFIG_CMD_IRQ
 164 #define CONFIG_CMD_MII
 165 #define CONFIG_CMD_NET
 166 #define CONFIG_CMD_PCI
 167 #define CONFIG_CMD_PING
 168 #define CONFIG_CMD_REGINFO
 169 #define CONFIG_CMD_SDRAM
 170 #define CONFIG_CMD_SNTP
 171
 172
 173 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 174
 175 #define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
 176
 177 /*
 178  * Miscellaneous configurable options
 179  */
 180 #define CFG_LONGHELP                    /* undef to save memory         */
 181 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 182 #if defined(CONFIG_CMD_KGDB)
 183 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 184 #else
 185 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 186 #endif
 187 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 188 #define CFG_MAXARGS     16              /* max number of command args   */
 189 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 190
 191 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 192 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 193
 194 /*
 195  * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 196  * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
 197  * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
 198  * The Linux BASE_BAUD define should match this configuration.
 199  *    baseBaud = cpuClock/(uartDivisor*16)
 200  * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
 201  * set Linux BASE_BAUD to 403200.
 202  */
 203 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 204 #undef  CFG_EXT_SERIAL_CLOCK           /* external serial clock */
 205 #undef  CFG_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
 206 #define CFG_BASE_BAUD       691200
 207
 208 /* The following table includes the supported baudrates */
 209 #define CFG_BAUDRATE_TABLE  \
 210     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 211
 212 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 213 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 214
 215 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 216
 217 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 218 #define CONFIG_LOOPW            1       /* enable loopw command         */
 219 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 220 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 221 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 222
 223 /*-----------------------------------------------------------------------
 224  * I2C stuff
 225  *-----------------------------------------------------------------------
 226  */
 227 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 228 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 229 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 230 #define CFG_I2C_SLAVE           0x7F
 231
 232 #define CFG_I2C_NOPROBES        { 0x69 }        /* avoid iprobe hangup (why?) */
 233 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  6       /* 24C02 requires 5ms delay */
 234
 235 #if defined(CONFIG_CMD_EEPROM)
 236 #define CFG_I2C_EEPROM_ADDR     0x50    /* I2C boot EEPROM (24C02W)     */
 237 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 238 #endif
 239
 240 /*-----------------------------------------------------------------------
 241  * PCI stuff
 242  *-----------------------------------------------------------------------
 243  */
 244 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 245 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 246 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 247
 248 #define CONFIG_PCI                      /* include pci support          */
 249 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 250 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 251                                         /* resource configuration       */
 252 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 253
 254 #define CFG_PCI_SUBSYS_VENDORID 0x10e8  /* AMCC */
 255 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */
 256 #define CFG_PCI_CLASSCODE       0x0600  /* PCI Class Code: bridge/host  */
 257 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 258 #define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
 259 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 260 #define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
 261 #define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
 262 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 263
 264 /*-----------------------------------------------------------------------
 265  * External peripheral base address
 266  *-----------------------------------------------------------------------
 267  */
 268 #define CFG_KEY_REG_BASE_ADDR   0xF0100000
 269 #define CFG_IR_REG_BASE_ADDR    0xF0200000
 270 #define CFG_FPGA_REG_BASE_ADDR  0xF0300000
 271
 272 /*-----------------------------------------------------------------------
 273  * Start addresses for the final memory configuration
 274  * (Set up by the startup code)
 275  * Please note that CFG_SDRAM_BASE _must_ start at 0
 276  */
 277 #define CFG_SDRAM_BASE          0x00000000
 278 #define CFG_SRAM_BASE           0xFFF00000
 279 #define CFG_FLASH_BASE          0xFFF80000
 280 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Monitor   */
 281 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserve 128 kB for malloc()  */
 282 #define CFG_MONITOR_BASE        (-CFG_MONITOR_LEN)
 283
 284 /*
 285  * For booting Linux, the board info and command line data
 286  * have to be in the first 8 MB of memory, since this is
 287  * the maximum mapped by the Linux kernel during initialization.
 288  */
 289 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 290
 291 /*-----------------------------------------------------------------------
 292  * FLASH organization
 293  */
 294 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 295 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 296
 297 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 298 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 299
 300 #define CFG_FLASH_ADDR0         0x5555
 301 #define CFG_FLASH_ADDR1         0x2aaa
 302 #define CFG_FLASH_WORD_SIZE     unsigned char
 303
 304 #ifdef CFG_ENV_IS_IN_FLASH
 305 #define CFG_ENV_SECT_SIZE       0x10000 /* size of one complete sector  */
 306 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 307 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 308
 309 /* Address and size of Redundant Environment Sector     */
 310 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 311 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 312 #endif /* CFG_ENV_IS_IN_FLASH */
 313
 314 /*-----------------------------------------------------------------------
 315  * NVRAM organization
 316  */
 317 #define CFG_NVRAM_BASE_ADDR     0xf0000000      /* NVRAM base address   */
 318 #define CFG_NVRAM_SIZE          0x1ff8          /* NVRAM size   */
 319
 320 #ifdef CFG_ENV_IS_IN_NVRAM
 321 #define CFG_ENV_SIZE            0x0ff8          /* Size of Environment vars     */
 322 #define CFG_ENV_ADDR            \
 323         (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)       /* Env  */
 324 #endif
 325
 326 /*
 327  * Init Memory Controller:
 328  *
 329  * BR0/1 and OR0/1 (FLASH)
 330  */
 331
 332 #define FLASH_BASE0_PRELIM      CFG_FLASH_BASE  /* FLASH bank #0        */
 333 #define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */
 334
 335 /*-----------------------------------------------------------------------
 336  * Definitions for initial stack pointer and data area (in data cache)
 337  */
 338 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 339 #define CFG_TEMP_STACK_OCM        1
 340
 341 /* On Chip Memory location */
 342 #define CFG_OCM_DATA_ADDR       0xF8000000
 343 #define CFG_OCM_DATA_SIZE       0x1000
 344 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR /* inside of SDRAM            */
 345 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE /* End of used area in RAM    */
 346
 347 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 348 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 349 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 350
 351 /*-----------------------------------------------------------------------
 352  * External Bus Controller (EBC) Setup
 353  */
 354
 355 /* Memory Bank 0 (Flash/SRAM) initialization                                    */
 356 #define CFG_EBC_PB0AP           0x04006000
 357 #define CFG_EBC_PB0CR           0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit  */
 358
 359 /* Memory Bank 1 (NVRAM/RTC) initialization                                     */
 360 #define CFG_EBC_PB1AP           0x04041000
 361 #define CFG_EBC_PB1CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 362
 363 /* Memory Bank 2 (not used) initialization                                      */
 364 #define CFG_EBC_PB2AP           0x00000000
 365 #define CFG_EBC_PB2CR           0x00000000
 366
 367 /* Memory Bank 2 (not used) initialization                                      */
 368 #define CFG_EBC_PB3AP           0x00000000
 369 #define CFG_EBC_PB3CR           0x00000000
 370
 371 /* Memory Bank 4 (FPGA regs) initialization                                     */
 372 #define CFG_EBC_PB4AP           0x01815000
 373 #define CFG_EBC_PB4CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
 374
 375 /*-----------------------------------------------------------------------
 376  * Definitions for Serial Presence Detect EEPROM address
 377  * (to get SDRAM settings)
 378  */
 379 #define SPD_EEPROM_ADDRESS      0x55
 380
 381 /*-----------------------------------------------------------------------
 382  * Definitions for GPIO setup (PPC405EP specific)
 383  *
 384  * GPIO0[0]     - External Bus Controller BLAST output
 385  * GPIO0[1-9]   - Instruction trace outputs
 386  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 387  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
 388  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 389  * GPIO0[24-27] - UART0 control signal inputs/outputs
 390  * GPIO0[28-29] - UART1 data signal input/output
 391  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 392  */
 393 #define CFG_GPIO0_OSRH          0x55555555
 394 #define CFG_GPIO0_OSRL          0x40000110
 395 #define CFG_GPIO0_ISR1H         0x00000000
 396 #define CFG_GPIO0_ISR1L         0x15555445
 397 #define CFG_GPIO0_TSRH          0x00000000
 398 #define CFG_GPIO0_TSRL          0x00000000
 399 #define CFG_GPIO0_TCR           0xFFFF8014
 400
 401 /*-----------------------------------------------------------------------
 402  * Some BUBINGA stuff...
 403  */
 404 #define NVRAM_BASE      0xF0000000
 405 #define FPGA_REG0       0xF0300000    /* FPGA Reg 0              */
 406 #define FPGA_REG1       0xF0300001    /* FPGA Reg 1              */
 407 #define NVRVFY1     0x4f532d4f    /* used to determine if state data in */
 408 #define NVRVFY2     0x50454e00    /* NVRAM initialized (ascii for OS-OPEN)*/
 409
 410 #define FPGA_REG0_F_RANGE     0x80       /* SDRAM PLL freq range              */
 411 #define FPGA_REG0_EXT_INT_DIS 0x20       /* External interface disable        */
 412 #define FPGA_REG0_LED_MASK    0x07       /* Board LEDs DS9, DS10, and DS11    */
 413 #define FPGA_REG0_LED0        0x04       /* Turn on LED0                      */
 414 #define FPGA_REG0_LED1        0x02       /* Turn on LED1                      */
 415 #define FPGA_REG0_LED2        0x01       /* Turn on LED2                      */
 416
 417 #define FPGA_REG1_SSPEC_DIS   0x80       /* C9531 Spread Spectrum disabled    */
 418 #define FPGA_REG1_OFFBD_PCICLK 0x40      /* Onboard PCI clock selected       */
 419 #define FPGA_REG1_CLOCK_MASK  0x30       /* Mask for C9531 output freq select */
 420 #define FPGA_REG1_CLOCK_BIT_SHIFT  4
 421 #define FPGA_REG1_PCI_INT_ARB 0x08       /* PCI Internal arbiter selected     */
 422 #define FPGA_REG1_PCI_FREQ    0x04       /* PCI Frequency select              */
 423 #define FPGA_REG1_OFFB_FLASH  0x02       /* Off board flash                   */
 424 #define FPGA_REG1_SRAM_BOOT   0x01       /* SRAM at 0xFFF80000 not Flash      */
 425
 426 /*
 427  * Internal Definitions
 428  *
 429  * Boot Flags
 430  */
 431 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 432 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 433
 434 #if defined(CONFIG_CMD_KGDB)
 435 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 436 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 437 #endif
 438
 439 /* pass open firmware flat tree */
 440 #define CONFIG_OF_LIBFDT        1
 441 #define CONFIG_OF_BOARD_SETUP   1
 442
 443 #endif  /* __CONFIG_H */