include/configs/canyonlands.h

   1 /*
   2  * (C) Copyright 2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 /************************************************************************
  22  * canyonlands.h - configuration for Canyonlands (460EX)
  23  ***********************************************************************/
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*-----------------------------------------------------------------------
  28  * High Level Configuration Options
  29  *----------------------------------------------------------------------*/
  30 /* This config file is used for Canyonlands (460EX) and Glacier (460GT) */
  31 #ifndef CONFIG_CANYONLANDS
  32 #define CONFIG_460GT            1       /* Specific PPC460GT            */
  33 #define CONFIG_HOSTNAME         glacier
  34 #else
  35 #define CONFIG_460EX            1       /* Specific PPC460EX            */
  36 #define CONFIG_HOSTNAME         canyonlands
  37 #endif
  38 #define CONFIG_440              1
  39 #define CONFIG_4xx              1       /* ... PPC4xx family */
  40
  41 /*
  42  * Include common defines/options for all AMCC eval boards
  43  */
  44 #include "amcc-common.h"
  45
  46 #define CONFIG_SYS_CLK_FREQ     66666667        /* external freq to pll */
  47
  48 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_early_init_f */
  49 #define CONFIG_BOARD_EARLY_INIT_R       1       /* Call board_early_init_r */
  50 #define CONFIG_MISC_INIT_R              1       /* Call misc_init_r */
  51 #define CONFIG_BOARD_TYPES              1       /* support board types */
  52
  53 /*-----------------------------------------------------------------------
  54  * Base addresses -- Note these are effective addresses where the
  55  * actual resources get mapped (not physical addresses)
  56  *----------------------------------------------------------------------*/
  57 #define CFG_PCI_MEMBASE         0x80000000      /* mapped PCI memory    */
  58 #define CFG_PCI_BASE            0xd0000000      /* internal PCI regs    */
  59 #define CFG_PCI_TARGBASE        CFG_PCI_MEMBASE
  60
  61 #define CFG_PCIE_MEMBASE        0xb0000000      /* mapped PCIe memory   */
  62 #define CFG_PCIE_MEMSIZE        0x08000000      /* smallest incr for PCIe port */
  63 #define CFG_PCIE_BASE           0xc4000000      /* PCIe UTL regs */
  64
  65 #define CFG_PCIE0_CFGBASE       0xc0000000
  66 #define CFG_PCIE1_CFGBASE       0xc1000000
  67 #define CFG_PCIE0_XCFGBASE      0xc3000000
  68 #define CFG_PCIE1_XCFGBASE      0xc3001000
  69
  70 #define CFG_PCIE0_UTLBASE       0xc08010000ULL  /* 36bit physical addr  */
  71
  72 /* base address of inbound PCIe window */
  73 #define CFG_PCIE_INBOUND_BASE   0x000000000ULL  /* 36bit physical addr  */
  74
  75 /* EBC stuff */
  76 #define CFG_NAND_ADDR           0xE0000000
  77 #define CFG_BCSR_BASE           0xE1000000
  78 #define CFG_BOOT_BASE_ADDR      0xFF000000      /* EBC Boot Space: 0xFF000000   */
  79 #define CFG_FLASH_BASE          0xFC000000      /* later mapped to this addr    */
  80 #define CFG_FLASH_BASE_PHYS_H   0x4
  81 #define CFG_FLASH_BASE_PHYS_L   0xCC000000
  82 #define CFG_FLASH_BASE_PHYS     (((u64)CFG_FLASH_BASE_PHYS_H << 32) | \
  83                                  (u64)CFG_FLASH_BASE_PHYS_L)
  84 #define CFG_FLASH_SIZE          (64 << 20)
  85
  86 #define CFG_OCM_BASE            0xE3000000      /* OCM: 16k             */
  87 #define CFG_SRAM_BASE           0xE8000000      /* SRAM: 256k           */
  88 #define CFG_LOCAL_CONF_REGS     0xEF000000
  89
  90 #define CFG_PERIPHERAL_BASE     0xEF600000      /* internal peripherals */
  91
  92 #define CFG_AHB_BASE            0xE2000000      /* internal AHB peripherals     */
  93
  94 /*-----------------------------------------------------------------------
  95  * Initial RAM & stack pointer (placed in OCM)
  96  *----------------------------------------------------------------------*/
  97 #define CFG_INIT_RAM_ADDR       CFG_OCM_BASE    /* OCM                  */
  98 #define CFG_INIT_RAM_END        (4 << 10)
  99 #define CFG_GBL_DATA_SIZE       256             /* num bytes initial data */
 100 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 101 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 102
 103 /*-----------------------------------------------------------------------
 104  * Serial Port
 105  *----------------------------------------------------------------------*/
 106 #undef CONFIG_UART1_CONSOLE     /* define this if you want console on UART1 */
 107
 108 /*-----------------------------------------------------------------------
 109  * Environment
 110  *----------------------------------------------------------------------*/
 111 /*
 112  * Define here the location of the environment variables (FLASH).
 113  */
 114 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 115 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
 116 #define CFG_NAND_CS             3       /* NAND chip connected to CSx */
 117 #else
 118 #define CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars  */
 119 #define CFG_NAND_CS             0       /* NAND chip connected to CSx */
 120 #define CONFIG_ENV_IS_EMBEDDED  1       /* use embedded environment */
 121 #endif
 122
 123 /*
 124  * IPL (Initial Program Loader, integrated inside CPU)
 125  * Will load first 4k from NAND (SPL) into cache and execute it from there.
 126  *
 127  * SPL (Secondary Program Loader)
 128  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 129  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 130  * controller and the NAND controller so that the special U-Boot image can be
 131  * loaded from NAND to SDRAM.
 132  *
 133  * NUB (NAND U-Boot)
 134  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 135  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 136  *
 137  * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 138  * set up. While still running from cache, I experienced problems accessing
 139  * the NAND controller. sr - 2006-08-25
 140  *
 141  * This is the first official implementation of booting from 2k page sized
 142  * NAND devices (e.g. Micron 29F2G08AA 256Mbit * 8)
 143  */
 144 #define CFG_NAND_BOOT_SPL_SRC   0xfffff000      /* SPL location               */
 145 #define CFG_NAND_BOOT_SPL_SIZE  (4 << 10)       /* SPL size                   */
 146 #define CFG_NAND_BOOT_SPL_DST   (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here  */
 147 #define CFG_NAND_U_BOOT_DST     0x01000000      /* Load NUB to this addr      */
 148 #define CFG_NAND_U_BOOT_START   CFG_NAND_U_BOOT_DST     /* Start NUB from     */
 149                                                         /*   this addr        */
 150 #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
 151
 152 /*
 153  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 154  */
 155 #define CFG_NAND_U_BOOT_OFFS    (128 << 10)     /* Offset to RAM U-Boot image */
 156 #define CFG_NAND_U_BOOT_SIZE    (1 << 20)       /* Size of RAM U-Boot image   */
 157
 158 /*
 159  * Now the NAND chip has to be defined (no autodetection used!)
 160  */
 161 #define CFG_NAND_PAGE_SIZE      (2 << 10)       /* NAND chip page size        */
 162 #define CFG_NAND_BLOCK_SIZE     (128 << 10)     /* NAND chip block size       */
 163 #define CFG_NAND_PAGE_COUNT     (CFG_NAND_BLOCK_SIZE / CFG_NAND_PAGE_SIZE)
 164                                                 /* NAND chip page count       */
 165 #define CFG_NAND_BAD_BLOCK_POS  0               /* Location of bad block marker*/
 166 #define CFG_NAND_5_ADDR_CYCLE                   /* Fifth addr used (<=128MB)  */
 167
 168 #define CFG_NAND_ECCSIZE        256
 169 #define CFG_NAND_ECCBYTES       3
 170 #define CFG_NAND_ECCSTEPS       (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
 171 #define CFG_NAND_OOBSIZE        64
 172 #define CFG_NAND_ECCTOTAL       (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
 173 #define CFG_NAND_ECCPOS         {40, 41, 42, 43, 44, 45, 46, 47, \
 174                                  48, 49, 50, 51, 52, 53, 54, 55, \
 175                                  56, 57, 58, 59, 60, 61, 62, 63}
 176
 177 #ifdef CONFIG_ENV_IS_IN_NAND
 178 /*
 179  * For NAND booting the environment is embedded in the U-Boot image. Please take
 180  * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
 181  */
 182 #define CONFIG_ENV_SIZE         CFG_NAND_BLOCK_SIZE
 183 #define CONFIG_ENV_OFFSET               (CFG_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 184 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 185 #endif
 186
 187 /*-----------------------------------------------------------------------
 188  * FLASH related
 189  *----------------------------------------------------------------------*/
 190 #define CFG_FLASH_CFI                   /* The flash is CFI compatible  */
 191 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 192 #define CFG_FLASH_CFI_AMD_RESET 1       /* Use AMD (Spansion) reset cmd */
 193
 194 #define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
 195 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 196 #define CFG_MAX_FLASH_SECT      512     /* max number of sectors on one chip    */
 197
 198 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 199 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 200
 201 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 202 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 203
 204 #ifdef CONFIG_ENV_IS_IN_FLASH
 205 #define CONFIG_ENV_SECT_SIZE    0x20000         /* size of one complete sector  */
 206 #define CONFIG_ENV_ADDR         (CFG_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 207 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 208
 209 /* Address and size of Redundant Environment Sector     */
 210 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 211 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 212 #endif /* CONFIG_ENV_IS_IN_FLASH */
 213
 214 /*-----------------------------------------------------------------------
 215  * NAND-FLASH related
 216  *----------------------------------------------------------------------*/
 217 #define CFG_MAX_NAND_DEVICE     1
 218 #define NAND_MAX_CHIPS          1
 219 #define CFG_NAND_BASE           (CFG_NAND_ADDR + CFG_NAND_CS)
 220 #define CFG_NAND_SELECT_DEVICE  1       /* nand driver supports mutipl. chips   */
 221
 222 /*------------------------------------------------------------------------------
 223  * DDR SDRAM
 224  *----------------------------------------------------------------------------*/
 225 #if !defined(CONFIG_NAND_U_BOOT)
 226 /*
 227  * NAND booting U-Boot version uses a fixed initialization, since the whole
 228  * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
 229  * code.
 230  */
 231 #define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
 232 #define SPD_EEPROM_ADDRESS      {0x50, 0x51}    /* SPD i2c spd addresses*/
 233 #define CONFIG_DDR_ECC          1       /* with ECC support             */
 234 #define CONFIG_DDR_RQDC_FIXED   0x80000038 /* fixed value for RQDC      */
 235 #endif
 236 #define CFG_MBYTES_SDRAM        512     /* 512MB                        */
 237
 238 /*-----------------------------------------------------------------------
 239  * I2C
 240  *----------------------------------------------------------------------*/
 241 #define CFG_I2C_SPEED           400000  /* I2C speed                    */
 242
 243 #define CFG_I2C_MULTI_EEPROMS
 244 #define CFG_I2C_EEPROM_ADDR             (0xa8>>1)
 245 #define CFG_I2C_EEPROM_ADDR_LEN         1
 246 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 247 #define CFG_EEPROM_PAGE_WRITE_BITS      3
 248 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10
 249
 250 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 251 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 252 #define CONFIG_DTT_AD7414       1               /* use AD7414           */
 253 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 254 #define CFG_DTT_MAX_TEMP        70
 255 #define CFG_DTT_LOW_TEMP        -30
 256 #define CFG_DTT_HYSTERESIS      3
 257
 258 /* RTC configuration */
 259 #define CONFIG_RTC_M41T62       1
 260 #define CFG_I2C_RTC_ADDR        0x68
 261
 262 /*-----------------------------------------------------------------------
 263  * Ethernet
 264  *----------------------------------------------------------------------*/
 265 #define CONFIG_IBM_EMAC4_V4     1
 266 #define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 267 #define CONFIG_PHY1_ADDR        1
 268 #define CONFIG_HAS_ETH0
 269 #define CONFIG_HAS_ETH1
 270 /* Only Glacier (460GT) has 4 EMAC interfaces */
 271 #ifdef CONFIG_460GT
 272 #define CONFIG_PHY2_ADDR        2
 273 #define CONFIG_PHY3_ADDR        3
 274 #define CONFIG_HAS_ETH2
 275 #define CONFIG_HAS_ETH3
 276 #endif
 277
 278 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 279 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 280 #define CONFIG_PHY_DYNAMIC_ANEG 1
 281
 282 /*-----------------------------------------------------------------------
 283  * USB-OHCI
 284  *----------------------------------------------------------------------*/
 285 /* Only Canyonlands (460EX) has USB */
 286 #ifdef CONFIG_460EX
 287 #define CONFIG_USB_OHCI_NEW
 288 #define CONFIG_USB_STORAGE
 289 #undef CFG_OHCI_BE_CONTROLLER           /* 460EX has little endian descriptors  */
 290 #define CFG_OHCI_SWAP_REG_ACCESS        /* 460EX has little endian register     */
 291 #define CFG_OHCI_USE_NPS                /* force NoPowerSwitching mode          */
 292 #define CFG_USB_OHCI_REGS_BASE  (CFG_AHB_BASE | 0xd0000)
 293 #define CFG_USB_OHCI_SLOT_NAME  "ppc440"
 294 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15
 295 #endif
 296
 297 /*
 298  * Default environment variables
 299  */
 300 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 301         CONFIG_AMCC_DEF_ENV                                             \
 302         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 303         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 304         CONFIG_AMCC_DEF_ENV_NAND_UPD                                    \
 305         "kernel_addr=fc000000\0"                                        \
 306         "fdt_addr=fc1e0000\0"                                           \
 307         "ramdisk_addr=fc200000\0"                                       \
 308         "pciconfighost=1\0"                                             \
 309         "pcie_mode=RP:RP\0"                                             \
 310         ""
 311
 312 /*
 313  * Commands additional to the ones defined in amcc-common.h
 314  */
 315 #define CONFIG_CMD_DATE
 316 #define CONFIG_CMD_DTT
 317 #define CONFIG_CMD_NAND
 318 #define CONFIG_CMD_PCI
 319 #define CONFIG_CMD_SDRAM
 320 #define CONFIG_CMD_SNTP
 321 #ifdef CONFIG_460EX
 322 #define CONFIG_CMD_EXT2
 323 #define CONFIG_CMD_FAT
 324 #define CONFIG_CMD_USB
 325 #endif
 326
 327 /* Partitions */
 328 #define CONFIG_MAC_PARTITION
 329 #define CONFIG_DOS_PARTITION
 330 #define CONFIG_ISO_PARTITION
 331
 332 /*-----------------------------------------------------------------------
 333  * PCI stuff
 334  *----------------------------------------------------------------------*/
 335 /* General PCI */
 336 #define CONFIG_PCI                      /* include pci support          */
 337 #define CONFIG_PCI_PNP                  /* do pci plug-and-play   */
 338 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 339 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 340
 341 /* Board-specific PCI */
 342 #define CFG_PCI_TARGET_INIT             /* let board init pci target    */
 343 #undef  CFG_PCI_MASTER_INIT
 344
 345 #define CFG_PCI_SUBSYS_VENDORID 0x1014  /* IBM                          */
 346 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever                     */
 347
 348 /*-----------------------------------------------------------------------
 349  * External Bus Controller (EBC) Setup
 350  *----------------------------------------------------------------------*/
 351
 352 /*
 353  * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
 354  * boot EBC mapping only supports a maximum of 16MBytes
 355  * (4.ff00.0000 - 4.ffff.ffff).
 356  * To solve this problem, the FLASH has to get remapped to another
 357  * EBC address which accepts bigger regions:
 358  *
 359  * 0xfc00.0000 -> 4.cc00.0000
 360  */
 361
 362 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 363 /* Memory Bank 3 (NOR-FLASH) initialization                                     */
 364 #define CFG_EBC_PB3AP           0x10055e00
 365 #define CFG_EBC_PB3CR           (CFG_BOOT_BASE_ADDR | 0x9a000)
 366
 367 /* Memory Bank 0 (NAND-FLASH) initialization                                            */
 368 #define CFG_EBC_PB0AP           0x018003c0
 369 #define CFG_EBC_PB0CR           (CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
 370 #else
 371 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
 372 #define CFG_EBC_PB0AP           0x10055e00
 373 #define CFG_EBC_PB0CR           (CFG_BOOT_BASE_ADDR | 0x9a000)
 374
 375 /* Memory Bank 3 (NAND-FLASH) initialization                                            */
 376 #define CFG_EBC_PB3AP           0x018003c0
 377 #define CFG_EBC_PB3CR           (CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
 378 #endif
 379
 380 /* Memory Bank 2 (CPLD) initialization                                          */
 381 #define CFG_EBC_PB2AP           0x00804240
 382 #define CFG_EBC_PB2CR           (CFG_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
 383
 384 #define CFG_EBC_CFG             0xB8400000              /*  EBC0_CFG */
 385
 386 /*
 387  * PPC4xx GPIO Configuration
 388  */
 389 #ifdef CONFIG_460EX
 390 /* 460EX: Use USB configuration */
 391 #define CFG_4xx_GPIO_TABLE { /*   Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 392 {                                                                                       \
 393 /* GPIO Core 0 */                                                                       \
 394 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0)      USB2HostD(0)    */      \
 395 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1)      USB2HostD(1)    */      \
 396 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2)      USB2HostD(2)    */      \
 397 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3)      USB2HostD(3)    */      \
 398 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4)      USB2HostD(4)    */      \
 399 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5)      USB2HostD(5)    */      \
 400 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6)      USB2HostD(6)    */      \
 401 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7)      USB2HostD(7)    */      \
 402 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0)      USB2OTGD(0)     */      \
 403 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1)      USB2OTGD(1)     */      \
 404 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)     USB2OTGD(2)     */      \
 405 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)     USB2OTGD(3)     */      \
 406 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)     USB2OTGD(4)     */      \
 407 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)     USB2OTGD(5)     */      \
 408 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)     USB2OTGD(6)     */      \
 409 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)     USB2OTGD(7)     */      \
 410 {GPIO0_BASE, GPIO_IN , GPIO_SEL,  GPIO_OUT_0}, /* GPIO16 GMC1TxER       USB2HostStop    */      \
 411 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD         USB2HostNext    */      \
 412 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER       USB2HostDir     */      \
 413 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO19 GMC1TxEN       USB2OTGStop     */      \
 414 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS        USB2OTGNext     */      \
 415 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV       USB2OTGDir      */      \
 416 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                          */      \
 417 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                          */      \
 418 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                          */      \
 419 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE                          */      \
 420 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE                          */      \
 421 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)                         */      \
 422 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)                         */      \
 423 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)                         */      \
 424 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0        DMAReq2         IRQ(7)*/ \
 425 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1        DMAAck2         IRQ(8)*/ \
 426 },                                                                                      \
 427 {                                                                                       \
 428 /* GPIO Core 1 */                                                                       \
 429 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2        EOT2/TC2        IRQ(9)*/ \
 430 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3        DMAReq3         IRQ(4)*/ \
 431 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 432 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 433 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3       UART3_SIN*/ \
 434 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EOT3/TC3        UART3_SOUT*/ \
 435 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 436 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 437 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                         */      \
 438 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                          */      \
 439 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                          */      \
 440 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)          DMAReq1         IRQ(10)*/ \
 441 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)          DMAAck1         IRQ(11)*/ \
 442 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)          EOT/TC1         IRQ(12)*/ \
 443 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)     DMAReq0         IRQ(13)*/ \
 444 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)     DMAAck0         IRQ(14)*/ \
 445 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)     EOT/TC0         IRQ(15)*/ \
 446 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 447 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 448 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 449 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 450 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 451 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 452 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 453 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 454 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 455 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 456 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 457 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 458 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 459 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 460 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 461 }                                                                                       \
 462 }
 463 #else
 464 /* 460GT: Use EMAC2+3 configuration */
 465 #define CFG_4xx_GPIO_TABLE { /*   Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 466 {                                                                                       \
 467 /* GPIO Core 0 */                                                                       \
 468 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0)      USB2HostD(0)    */      \
 469 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1)      USB2HostD(1)    */      \
 470 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2)      USB2HostD(2)    */      \
 471 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3)      USB2HostD(3)    */      \
 472 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4)      USB2HostD(4)    */      \
 473 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5)      USB2HostD(5)    */      \
 474 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6)      USB2HostD(6)    */      \
 475 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7)      USB2HostD(7)    */      \
 476 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0)      USB2OTGD(0)     */      \
 477 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1)      USB2OTGD(1)     */      \
 478 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)     USB2OTGD(2)     */      \
 479 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)     USB2OTGD(3)     */      \
 480 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)     USB2OTGD(4)     */      \
 481 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)     USB2OTGD(5)     */      \
 482 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)     USB2OTGD(6)     */      \
 483 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)     USB2OTGD(7)     */      \
 484 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER       USB2HostStop    */      \
 485 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD         USB2HostNext    */      \
 486 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER       USB2HostDir     */      \
 487 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN       USB2OTGStop     */      \
 488 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS        USB2OTGNext     */      \
 489 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV       USB2OTGDir      */      \
 490 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                          */      \
 491 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                          */      \
 492 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                          */      \
 493 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE                          */      \
 494 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE                          */      \
 495 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)                         */      \
 496 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)                         */      \
 497 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)                         */      \
 498 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0        DMAReq2         IRQ(7)*/ \
 499 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1        DMAAck2         IRQ(8)*/ \
 500 },                                                                                      \
 501 {                                                                                       \
 502 /* GPIO Core 1 */                                                                       \
 503 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2        EOT2/TC2        IRQ(9)*/ \
 504 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3        DMAReq3         IRQ(4)*/ \
 505 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 506 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 507 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3       UART3_SIN*/ \
 508 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EOT3/TC3        UART3_SOUT*/ \
 509 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 510 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 511 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                         */      \
 512 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                          */      \
 513 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                          */      \
 514 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)          DMAReq1         IRQ(10)*/ \
 515 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)          DMAAck1         IRQ(11)*/ \
 516 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)          EOT/TC1         IRQ(12)*/ \
 517 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)     DMAReq0         IRQ(13)*/ \
 518 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)     DMAAck0         IRQ(14)*/ \
 519 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)     EOT/TC0         IRQ(15)*/ \
 520 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 521 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 522 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 523 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 524 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 525 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 526 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 527 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 528 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 529 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 530 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 531 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 532 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 533 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 534 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 535 }                                                                                       \
 536 }
 537 #endif
 538
 539 #endif  /* __CONFIG_H */