include/configs/canyonlands.h

   1 /*
   2  * (C) Copyright 2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 /************************************************************************
  22  * canyonlands.h - configuration for Canyonlands (460EX)
  23  ***********************************************************************/
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*-----------------------------------------------------------------------
  28  * High Level Configuration Options
  29  *----------------------------------------------------------------------*/
  30 /*
  31  * This config file is used for Canyonlands (460EX) Glacier (460GT)
  32  * and Arches dual (460GT)
  33  */
  34 #ifdef CONFIG_CANYONLANDS
  35 #define CONFIG_460EX            1       /* Specific PPC460EX            */
  36 #define CONFIG_HOSTNAME         canyonlands
  37 #else
  38 #define CONFIG_460GT            1       /* Specific PPC460GT            */
  39 #ifdef CONFIG_GLACIER
  40 #define CONFIG_HOSTNAME         glacier
  41 #else
  42 #define CONFIG_HOSTNAME         arches
  43 #define CONFIG_USE_NETDEV       eth1
  44 #define CONFIG_BD_NUM_CPUS      2
  45 #endif
  46 #endif
  47
  48 #define CONFIG_440              1
  49 #define CONFIG_4xx              1       /* ... PPC4xx family */
  50
  51 #ifndef CONFIG_SYS_TEXT_BASE
  52 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  53 #endif
  54
  55 /*
  56  * Include common defines/options for all AMCC eval boards
  57  */
  58 #include "amcc-common.h"
  59
  60 #define CONFIG_SYS_CLK_FREQ     66666667        /* external freq to pll */
  61
  62 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_early_init_f */
  63 #define CONFIG_BOARD_EARLY_INIT_R       1       /* Call board_early_init_r */
  64 #define CONFIG_MISC_INIT_R              1       /* Call misc_init_r */
  65 #define CONFIG_BOARD_TYPES              1       /* support board types */
  66
  67 /*-----------------------------------------------------------------------
  68  * Base addresses -- Note these are effective addresses where the
  69  * actual resources get mapped (not physical addresses)
  70  *----------------------------------------------------------------------*/
  71 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory    */
  72 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
  73 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
  74
  75 #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000      /* mapped PCIe memory   */
  76 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* smallest incr for PCIe port */
  77 #define CONFIG_SYS_PCIE_BASE            0xc4000000      /* PCIe UTL regs */
  78
  79 #define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
  80 #define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
  81 #define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
  82 #define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
  83
  84 /*
  85  * BCSR bits as defined in the Canyonlands board user manual.
  86  */
  87 #define BCSR_USBCTRL_OTG_RST    0x32
  88 #define BCSR_USBCTRL_HOST_RST   0x01
  89 #define BCSR_SELECT_PCIE        0x10
  90
  91 #define CONFIG_SYS_PCIE0_UTLBASE        0xc08010000ULL  /* 36bit physical addr  */
  92
  93 /* base address of inbound PCIe window */
  94 #define CONFIG_SYS_PCIE_INBOUND_BASE    0x000000000ULL  /* 36bit physical addr  */
  95
  96 /* EBC stuff */
  97 #if !defined(CONFIG_ARCHES)
  98 #define CONFIG_SYS_BCSR_BASE            0xE1000000
  99 #define CONFIG_SYS_FLASH_BASE           0xFC000000      /* later mapped to this addr */
 100 #define CONFIG_SYS_FLASH_SIZE           (64 << 20)
 101 #else
 102 #define CONFIG_SYS_FPGA_BASE            0xE1000000
 103 #define CONFIG_SYS_CPLD_ADDR            (CONFIG_SYS_FPGA_BASE + 0x00080000)
 104 #define CONFIG_SYS_CPLD_DATA            (CONFIG_SYS_FPGA_BASE + 0x00080002)
 105 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* later mapped to this addr  */
 106 #define CONFIG_SYS_FLASH_SIZE           (32 << 20)
 107 #endif
 108
 109 #define CONFIG_SYS_NAND_ADDR            0xE0000000
 110 #define CONFIG_SYS_BOOT_BASE_ADDR       0xFF000000      /* EBC Boot Space: 0xFF000000 */
 111 #define CONFIG_SYS_FLASH_BASE_PHYS_H    0x4
 112 #define CONFIG_SYS_FLASH_BASE_PHYS_L    0xCC000000
 113 #define CONFIG_SYS_FLASH_BASE_PHYS      (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) |    \
 114                                          (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
 115
 116 #define CONFIG_SYS_OCM_BASE             0xE3000000      /* OCM: 64k             */
 117 #define CONFIG_SYS_SRAM_BASE            0xE8000000      /* SRAM: 256k           */
 118 #define CONFIG_SYS_SRAM_SIZE            (256 << 10)
 119 #define CONFIG_SYS_LOCAL_CONF_REGS      0xEF000000
 120
 121 #define CONFIG_SYS_AHB_BASE             0xE2000000      /* internal AHB peripherals     */
 122
 123 /*-----------------------------------------------------------------------
 124  * Initial RAM & stack pointer (placed in OCM)
 125  *----------------------------------------------------------------------*/
 126 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
 127 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
 128 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 129 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 130
 131 /*-----------------------------------------------------------------------
 132  * Serial Port
 133  *----------------------------------------------------------------------*/
 134 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 135
 136 /*-----------------------------------------------------------------------
 137  * Environment
 138  *----------------------------------------------------------------------*/
 139 /*
 140  * Define here the location of the environment variables (FLASH).
 141  */
 142 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 143 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
 144 #define CONFIG_SYS_NOR_CS               0       /* NOR chip connected to CSx */
 145 #define CONFIG_SYS_NAND_CS              3       /* NAND chip connected to CSx */
 146 #else
 147 #define CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars  */
 148 #define CONFIG_SYS_NOR_CS               3       /* NOR chip connected to CSx */
 149 #define CONFIG_SYS_NAND_CS              0       /* NAND chip connected to CSx */
 150 #define CONFIG_ENV_IS_EMBEDDED  1       /* use embedded environment */
 151 #endif
 152
 153 /*
 154  * IPL (Initial Program Loader, integrated inside CPU)
 155  * Will load first 4k from NAND (SPL) into cache and execute it from there.
 156  *
 157  * SPL (Secondary Program Loader)
 158  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 159  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 160  * controller and the NAND controller so that the special U-Boot image can be
 161  * loaded from NAND to SDRAM.
 162  *
 163  * NUB (NAND U-Boot)
 164  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 165  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 166  *
 167  * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 168  * set up. While still running from cache, I experienced problems accessing
 169  * the NAND controller. sr - 2006-08-25
 170  *
 171  * This is the first official implementation of booting from 2k page sized
 172  * NAND devices (e.g. Micron 29F2G08AA 256Mbit * 8)
 173  */
 174 #define CONFIG_SYS_NAND_BOOT_SPL_SRC    0xfffff000      /* SPL location               */
 175 #define CONFIG_SYS_NAND_BOOT_SPL_SIZE   (4 << 10)       /* SPL size                   */
 176 #define CONFIG_SYS_NAND_BOOT_SPL_DST    (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here  */
 177 #define CONFIG_SYS_NAND_U_BOOT_DST      0x01000000      /* Load NUB to this addr      */
 178 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST      /* Start NUB from     */
 179                                                         /*   this addr        */
 180 #define CONFIG_SYS_NAND_BOOT_SPL_DELTA  (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 181
 182 /*
 183  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 184  */
 185 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)     /* Offset to RAM U-Boot image */
 186 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (1 << 20)       /* Size of RAM U-Boot image   */
 187
 188 /*
 189  * Now the NAND chip has to be defined (no autodetection used!)
 190  */
 191 #define CONFIG_SYS_NAND_PAGE_SIZE       (2 << 10)       /* NAND chip page size        */
 192 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)     /* NAND chip block size       */
 193 #define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)
 194                                                 /* NAND chip page count       */
 195 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0               /* Location of bad block marker*/
 196 #define CONFIG_SYS_NAND_5_ADDR_CYCLE                    /* Fifth addr used (<=128MB)  */
 197
 198 #define CONFIG_SYS_NAND_ECCSIZE 256
 199 #define CONFIG_SYS_NAND_ECCBYTES        3
 200 #define CONFIG_SYS_NAND_ECCSTEPS        (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
 201 #define CONFIG_SYS_NAND_OOBSIZE 64
 202 #define CONFIG_SYS_NAND_ECCTOTAL        (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
 203 #define CONFIG_SYS_NAND_ECCPOS          {40, 41, 42, 43, 44, 45, 46, 47, \
 204                                  48, 49, 50, 51, 52, 53, 54, 55, \
 205                                  56, 57, 58, 59, 60, 61, 62, 63}
 206
 207 #ifdef CONFIG_ENV_IS_IN_NAND
 208 /*
 209  * For NAND booting the environment is embedded in the U-Boot image. Please take
 210  * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
 211  */
 212 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 213 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 214 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 215 #endif
 216
 217 /*-----------------------------------------------------------------------
 218  * FLASH related
 219  *----------------------------------------------------------------------*/
 220 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 221 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 222 #define CONFIG_SYS_FLASH_CFI_AMD_RESET  1       /* Use AMD (Spansion) reset cmd */
 223
 224 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 225 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 226 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 227
 228 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 229 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 230
 231 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 232 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 233
 234 #ifdef CONFIG_ENV_IS_IN_FLASH
 235 #define CONFIG_ENV_SECT_SIZE    0x20000         /* size of one complete sector  */
 236 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 237 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 238
 239 /* Address and size of Redundant Environment Sector     */
 240 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 241 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 242 #endif /* CONFIG_ENV_IS_IN_FLASH */
 243
 244 /*-----------------------------------------------------------------------
 245  * NAND-FLASH related
 246  *----------------------------------------------------------------------*/
 247 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 248 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 249 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips   */
 250
 251 /*------------------------------------------------------------------------------
 252  * DDR SDRAM
 253  *----------------------------------------------------------------------------*/
 254 #if !defined(CONFIG_NAND_U_BOOT)
 255 #if !defined(CONFIG_ARCHES)
 256 /*
 257  * NAND booting U-Boot version uses a fixed initialization, since the whole
 258  * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
 259  * code.
 260  */
 261 #define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
 262 #define SPD_EEPROM_ADDRESS      {0x50, 0x51}    /* SPD i2c spd addresses*/
 263 #define CONFIG_DDR_ECC          1       /* with ECC support             */
 264 #define CONFIG_DDR_RQDC_FIXED   0x80000038 /* fixed value for RQDC      */
 265
 266 #else /* defined(CONFIG_ARCHES) */
 267
 268 #define CONFIG_AUTOCALIB        "silent\0"      /* default is non-verbose    */
 269
 270 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration   */
 271 #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
 272 #undef CONFIG_PPC4xx_DDR_METHOD_A
 273
 274 /* DDR1/2 SDRAM Device Control Register Data Values */
 275 /* Memory Queue */
 276 #define CONFIG_SYS_SDRAM_R0BAS          0x0000f000
 277 #define CONFIG_SYS_SDRAM_R1BAS          0x00000000
 278 #define CONFIG_SYS_SDRAM_R2BAS          0x00000000
 279 #define CONFIG_SYS_SDRAM_R3BAS          0x00000000
 280 #define CONFIG_SYS_SDRAM_PLBADDULL      0x00000000
 281 #define CONFIG_SYS_SDRAM_PLBADDUHB      0x00000008
 282 #define CONFIG_SYS_SDRAM_CONF1LL        0x00001080
 283 #define CONFIG_SYS_SDRAM_CONF1HB        0x00001080
 284 #define CONFIG_SYS_SDRAM_CONFPATHB      0x10a68000
 285
 286 /* SDRAM Controller */
 287 #define CONFIG_SYS_SDRAM0_MB0CF         0x00000701
 288 #define CONFIG_SYS_SDRAM0_MB1CF         0x00000000
 289 #define CONFIG_SYS_SDRAM0_MB2CF         0x00000000
 290 #define CONFIG_SYS_SDRAM0_MB3CF         0x00000000
 291 #define CONFIG_SYS_SDRAM0_MCOPT1        0x05322000
 292 #define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
 293 #define CONFIG_SYS_SDRAM0_MODT0         0x01000000
 294 #define CONFIG_SYS_SDRAM0_MODT1         0x00000000
 295 #define CONFIG_SYS_SDRAM0_MODT2         0x00000000
 296 #define CONFIG_SYS_SDRAM0_MODT3         0x00000000
 297 #define CONFIG_SYS_SDRAM0_CODT          0x00800021
 298 #define CONFIG_SYS_SDRAM0_RTR           0x06180000
 299 #define CONFIG_SYS_SDRAM0_INITPLR0      0xb5380000
 300 #define CONFIG_SYS_SDRAM0_INITPLR1      0x82100400
 301 #define CONFIG_SYS_SDRAM0_INITPLR2      0x80820000
 302 #define CONFIG_SYS_SDRAM0_INITPLR3      0x80830000
 303 #define CONFIG_SYS_SDRAM0_INITPLR4      0x80810040
 304 #define CONFIG_SYS_SDRAM0_INITPLR5      0x80800532
 305 #define CONFIG_SYS_SDRAM0_INITPLR6      0x82100400
 306 #define CONFIG_SYS_SDRAM0_INITPLR7      0x8a080000
 307 #define CONFIG_SYS_SDRAM0_INITPLR8      0x8a080000
 308 #define CONFIG_SYS_SDRAM0_INITPLR9      0x8a080000
 309 #define CONFIG_SYS_SDRAM0_INITPLR10     0x8a080000
 310 #define CONFIG_SYS_SDRAM0_INITPLR11     0x80000432
 311 #define CONFIG_SYS_SDRAM0_INITPLR12     0x808103c0
 312 #define CONFIG_SYS_SDRAM0_INITPLR13     0x80810040
 313 #define CONFIG_SYS_SDRAM0_INITPLR14     0x00000000
 314 #define CONFIG_SYS_SDRAM0_INITPLR15     0x00000000
 315 #define CONFIG_SYS_SDRAM0_RQDC          0x80000038
 316 #define CONFIG_SYS_SDRAM0_RFDC          0x00000257
 317 #define CONFIG_SYS_SDRAM0_RDCC          0x40000000
 318 #define CONFIG_SYS_SDRAM0_DLCR          0x03000091
 319 #define CONFIG_SYS_SDRAM0_CLKTR         0x40000000
 320 #define CONFIG_SYS_SDRAM0_WRDTR         0x82000823
 321 #define CONFIG_SYS_SDRAM0_SDTR1         0x80201000
 322 #define CONFIG_SYS_SDRAM0_SDTR2         0x42204243
 323 #define CONFIG_SYS_SDRAM0_SDTR3         0x090c0d1a
 324 #define CONFIG_SYS_SDRAM0_MMODE         0x00000432
 325 #define CONFIG_SYS_SDRAM0_MEMODE        0x00000004
 326 #endif  /* !defined(CONFIG_ARCHES) */
 327 #endif  /* !defined(CONFIG_NAND_U_BOOT) */
 328
 329 #define CONFIG_SYS_MBYTES_SDRAM 512     /* 512MB                        */
 330
 331 /*-----------------------------------------------------------------------
 332  * I2C
 333  *----------------------------------------------------------------------*/
 334 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed                    */
 335
 336 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 337 #define CONFIG_SYS_I2C_EEPROM_ADDR              (0xa8>>1)
 338 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 339 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 340 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 341
 342 /* I2C bootstrap EEPROM */
 343 #if defined(CONFIG_ARCHES)
 344 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x54
 345 #else
 346 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
 347 #endif
 348 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 349 #define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 350
 351 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 352 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 353 #define CONFIG_DTT_AD7414       1               /* use AD7414           */
 354 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 355 #define CONFIG_SYS_DTT_MAX_TEMP 70
 356 #define CONFIG_SYS_DTT_LOW_TEMP -30
 357 #define CONFIG_SYS_DTT_HYSTERESIS       3
 358
 359 #if defined(CONFIG_ARCHES)
 360 #define CONFIG_SYS_I2C_DTT_ADDR 0x4a            /* AD7414 I2C address   */
 361 #endif
 362
 363 #if !defined(CONFIG_ARCHES)
 364 /* RTC configuration */
 365 #define CONFIG_RTC_M41T62       1
 366 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 367 #endif
 368
 369 /*-----------------------------------------------------------------------
 370  * Ethernet
 371  *----------------------------------------------------------------------*/
 372 #define CONFIG_IBM_EMAC4_V4     1
 373
 374 #define CONFIG_HAS_ETH0
 375 #define CONFIG_HAS_ETH1
 376
 377 #if !defined(CONFIG_ARCHES)
 378 #define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 379 #define CONFIG_PHY1_ADDR        1
 380 /* Only Glacier (460GT) has 4 EMAC interfaces */
 381 #ifdef CONFIG_460GT
 382 #define CONFIG_PHY2_ADDR        2
 383 #define CONFIG_PHY3_ADDR        3
 384 #define CONFIG_HAS_ETH2
 385 #define CONFIG_HAS_ETH3
 386 #endif
 387
 388 #else /* defined(CONFIG_ARCHES) */
 389
 390 #define CONFIG_FIXED_PHY        0xFFFFFFFF
 391 #define CONFIG_PHY_ADDR         CONFIG_FIXED_PHY
 392 #define CONFIG_PHY1_ADDR        0
 393 #define CONFIG_PHY2_ADDR        1
 394 #define CONFIG_HAS_ETH2
 395
 396 #define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
 397                 {devnum, speed, duplex}
 398 #define CONFIG_SYS_FIXED_PHY_PORTS \
 399                 CONFIG_SYS_FIXED_PHY_PORT(0, 1000, FULL)
 400
 401 #define CONFIG_M88E1112_PHY
 402
 403 /*
 404  * For the GPCS_PHYx_ADDR PHY address, choose some PHY address not
 405  * used by CONFIG_PHYx_ADDR
 406  */
 407 #define CONFIG_GPCS_PHY_ADDR    0xA
 408 #define CONFIG_GPCS_PHY1_ADDR   0xB
 409 #define CONFIG_GPCS_PHY2_ADDR   0xC
 410 #endif  /* !defined(CONFIG_ARCHES) */
 411
 412 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 413 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 414 #define CONFIG_PHY_DYNAMIC_ANEG 1
 415
 416 /*-----------------------------------------------------------------------
 417  * USB-OHCI
 418  *----------------------------------------------------------------------*/
 419 /* Only Canyonlands (460EX) has USB */
 420 #ifdef CONFIG_460EX
 421 #define CONFIG_USB_OHCI_NEW
 422 #define CONFIG_USB_STORAGE
 423 #undef CONFIG_SYS_OHCI_BE_CONTROLLER            /* 460EX has little endian descriptors  */
 424 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register     */
 425 #define CONFIG_SYS_OHCI_USE_NPS         /* force NoPowerSwitching mode          */
 426 #define CONFIG_SYS_USB_OHCI_REGS_BASE   (CONFIG_SYS_AHB_BASE | 0xd0000)
 427 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 428 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 429 #define CONFIG_SYS_USB_OHCI_BOARD_INIT
 430 #endif
 431
 432 /*
 433  * Default environment variables
 434  */
 435 #if !defined(CONFIG_ARCHES)
 436 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 437         CONFIG_AMCC_DEF_ENV                                             \
 438         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 439         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 440         CONFIG_AMCC_DEF_ENV_NAND_UPD                                    \
 441         "kernel_addr=fc000000\0"                                        \
 442         "fdt_addr=fc1e0000\0"                                           \
 443         "ramdisk_addr=fc200000\0"                                       \
 444         "pciconfighost=1\0"                                             \
 445         "pcie_mode=RP:RP\0"                                             \
 446         ""
 447 #else /* defined(CONFIG_ARCHES) */
 448 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 449         CONFIG_AMCC_DEF_ENV                                             \
 450         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 451         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 452         "kernel_addr=fe000000\0"                                        \
 453         "fdt_addr=fe1e0000\0"                                           \
 454         "ramdisk_addr=fe200000\0"                                       \
 455         "pciconfighost=1\0"                                             \
 456         "pcie_mode=RP:RP\0"                                             \
 457         "ethprime=ppc_4xx_eth1\0"                                       \
 458         ""
 459 #endif  /* !defined(CONFIG_ARCHES) */
 460
 461 /*
 462  * Commands additional to the ones defined in amcc-common.h
 463  */
 464 #define CONFIG_CMD_CHIP_CONFIG
 465 #if defined(CONFIG_ARCHES)
 466 #define CONFIG_CMD_DTT
 467 #define CONFIG_CMD_PCI
 468 #define CONFIG_CMD_SDRAM
 469 #elif defined(CONFIG_CANYONLANDS)
 470 #define CONFIG_CMD_DATE
 471 #define CONFIG_CMD_DTT
 472 #define CONFIG_CMD_EXT2
 473 #define CONFIG_CMD_FAT
 474 #define CONFIG_CMD_NAND
 475 #define CONFIG_CMD_PCI
 476 #define CONFIG_CMD_SATA
 477 #define CONFIG_CMD_SDRAM
 478 #define CONFIG_CMD_SNTP
 479 #define CONFIG_CMD_USB
 480 #elif defined(CONFIG_GLACIER)
 481 #define CONFIG_CMD_DATE
 482 #define CONFIG_CMD_DTT
 483 #define CONFIG_CMD_NAND
 484 #define CONFIG_CMD_PCI
 485 #define CONFIG_CMD_SDRAM
 486 #define CONFIG_CMD_SNTP
 487 #else
 488 #error "board type not defined"
 489 #endif
 490
 491 /* Partitions */
 492 #define CONFIG_MAC_PARTITION
 493 #define CONFIG_DOS_PARTITION
 494 #define CONFIG_ISO_PARTITION
 495
 496 /*-----------------------------------------------------------------------
 497  * PCI stuff
 498  *----------------------------------------------------------------------*/
 499 /* General PCI */
 500 #define CONFIG_PCI                      /* include pci support          */
 501 #define CONFIG_PCI_PNP                  /* do pci plug-and-play   */
 502 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 503 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 504
 505 /* Board-specific PCI */
 506 #define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
 507 #undef  CONFIG_SYS_PCI_MASTER_INIT
 508
 509 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM                          */
 510 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever                     */
 511
 512 #ifdef CONFIG_460GT
 513 #if defined(CONFIG_ARCHES)
 514 /*-----------------------------------------------------------------------
 515  * RapidIO I/O and Registers
 516  *----------------------------------------------------------------------*/
 517 #define CONFIG_RAPIDIO
 518 #define CONFIG_SYS_460GT_SRIO_ERRATA_1
 519
 520 #define SRGPL0_REG_BAR          0x0000000DAA000000ull   /*  16MB */
 521 #define SRGPL0_CFG_BAR          0x0000000DAB000000ull   /*  16MB */
 522 #define SRGPL0_MNT_BAR          0x0000000DAC000000ull   /*  16MB */
 523 #define SRGPL0_MSG_BAR          0x0000000DAD000000ull   /*  16MB */
 524 #define SRGPL0_OUT_BAR          0x0000000DB0000000ull   /* 256MB */
 525
 526 #define CONFIG_SYS_SRGPL0_REG_BAR       0xAA000000              /*  16MB */
 527 #define CONFIG_SYS_SRGPL0_CFG_BAR       0xAB000000              /*  16MB */
 528 #define CONFIG_SYS_SRGPL0_MNT_BAR       0xAC000000              /*  16MB */
 529 #define CONFIG_SYS_SRGPL0_MSG_BAR       0xAD000000              /*  16MB */
 530
 531 #define CONFIG_SYS_I2ODMA_BASE          0xCF000000
 532 #define CONFIG_SYS_I2ODMA_PHYS_ADDR     0x0000000400100000ull
 533
 534 #define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
 535 #undef CONFIG_PPC4XX_RAPIDIO_DEBUG
 536 #undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
 537 #define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
 538 #undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
 539 #endif /* CONFIG_ARCHES */
 540 #endif /* CONFIG_460GT */
 541
 542 /*
 543  * SATA driver setup
 544  */
 545 #ifdef CONFIG_CMD_SATA
 546 #define CONFIG_SATA_DWC
 547 #define CONFIG_LIBATA
 548 #define SATA_BASE_ADDR          0xe20d1000      /* PPC460EX SATA Base Address */
 549 #define SATA_DMA_REG_ADDR       0xe20d0800      /* PPC460EX SATA Base Address */
 550 #define CONFIG_SYS_SATA_MAX_DEVICE      1       /* SATA MAX DEVICE */
 551 /* Convert sectorsize to wordsize */
 552 #define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
 553 #endif
 554
 555 /*-----------------------------------------------------------------------
 556  * External Bus Controller (EBC) Setup
 557  *----------------------------------------------------------------------*/
 558
 559 /*
 560  * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
 561  * boot EBC mapping only supports a maximum of 16MBytes
 562  * (4.ff00.0000 - 4.ffff.ffff).
 563  * To solve this problem, the FLASH has to get remapped to another
 564  * EBC address which accepts bigger regions:
 565  *
 566  * 0xfc00.0000 -> 4.cc00.0000
 567  *
 568  * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), it will be
 569  * remapped to:
 570  *
 571  * 0xfe00.0000 -> 4.ce00.0000
 572  */
 573
 574 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 575 /* Memory Bank 3 (NOR-FLASH) initialization                                     */
 576 #define CONFIG_SYS_EBC_PB3AP            0x10055e00
 577 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
 578
 579 /* Memory Bank 0 (NAND-FLASH) initialization                                            */
 580 #define CONFIG_SYS_EBC_PB0AP            0x018003c0
 581 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
 582 #else
 583 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
 584 #define CONFIG_SYS_EBC_PB0AP            0x10055e00
 585 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
 586
 587 #if !defined(CONFIG_ARCHES)
 588 /* Memory Bank 3 (NAND-FLASH) initialization                                            */
 589 #define CONFIG_SYS_EBC_PB3AP            0x018003c0
 590 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
 591 #endif
 592 #endif  /*defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
 593
 594 #if !defined(CONFIG_ARCHES)
 595 /* Memory Bank 2 (CPLD) initialization                                          */
 596 #define CONFIG_SYS_EBC_PB2AP            0x00804240
 597 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
 598
 599 #else /* defined(CONFIG_ARCHES) */
 600
 601 /* Memory Bank 1 (FPGA) initialization  */
 602 #define CONFIG_SYS_EBC_PB1AP            0x7f8ffe80
 603 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
 604 #endif  /* !defined(CONFIG_ARCHES) */
 605
 606 #define CONFIG_SYS_EBC_CFG              0xbfc00000
 607
 608 /*
 609  * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
 610  * pin multiplexing correctly
 611  */
 612 #if defined(CONFIG_ARCHES)
 613 #define GPIO43_USE              GPIO_SEL        /* On Arches this pin is used as GPIO */
 614 #else
 615 #define GPIO43_USE              GPIO_ALT1       /* On Glacier this pin is used as ALT1 -> PerCS3 */
 616 #endif
 617
 618 /*
 619  * PPC4xx GPIO Configuration
 620  */
 621 #ifdef CONFIG_460EX
 622 /* 460EX: Use USB configuration */
 623 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 624 {                                                                                       \
 625 /* GPIO Core 0 */                                                                       \
 626 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0)      USB2HostD(0)    */      \
 627 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1)      USB2HostD(1)    */      \
 628 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2)      USB2HostD(2)    */      \
 629 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3)      USB2HostD(3)    */      \
 630 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4)      USB2HostD(4)    */      \
 631 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5)      USB2HostD(5)    */      \
 632 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6)      USB2HostD(6)    */      \
 633 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7)      USB2HostD(7)    */      \
 634 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0)      USB2OTGD(0)     */      \
 635 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1)      USB2OTGD(1)     */      \
 636 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)     USB2OTGD(2)     */      \
 637 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)     USB2OTGD(3)     */      \
 638 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)     USB2OTGD(4)     */      \
 639 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)     USB2OTGD(5)     */      \
 640 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)     USB2OTGD(6)     */      \
 641 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)     USB2OTGD(7)     */      \
 642 {GPIO0_BASE, GPIO_IN , GPIO_SEL,  GPIO_OUT_0}, /* GPIO16 GMC1TxER       USB2HostStop    */      \
 643 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD         USB2HostNext    */      \
 644 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER       USB2HostDir     */      \
 645 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO19 GMC1TxEN       USB2OTGStop     */      \
 646 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS        USB2OTGNext     */      \
 647 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV       USB2OTGDir      */      \
 648 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                          */      \
 649 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                          */      \
 650 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                          */      \
 651 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE                          */      \
 652 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE                          */      \
 653 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)                         */      \
 654 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)                         */      \
 655 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)                         */      \
 656 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0        DMAReq2         IRQ(7)*/ \
 657 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1        DMAAck2         IRQ(8)*/ \
 658 },                                                                                      \
 659 {                                                                                       \
 660 /* GPIO Core 1 */                                                                       \
 661 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2        EOT2/TC2        IRQ(9)*/ \
 662 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3        DMAReq3         IRQ(4)*/ \
 663 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 664 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 665 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3       UART3_SIN*/ \
 666 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EOT3/TC3        UART3_SOUT*/ \
 667 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 668 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 669 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                         */      \
 670 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                          */      \
 671 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                          */      \
 672 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)          DMAReq1         IRQ(10)*/ \
 673 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)          DMAAck1         IRQ(11)*/ \
 674 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)          EOT/TC1         IRQ(12)*/ \
 675 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)     DMAReq0         IRQ(13)*/ \
 676 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)     DMAAck0         IRQ(14)*/ \
 677 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)     EOT/TC0         IRQ(15)*/ \
 678 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 679 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 680 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 681 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 682 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 683 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 684 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 685 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 686 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 687 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 688 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 689 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 690 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 691 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 692 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 693 }                                                                                       \
 694 }
 695 #else
 696 /* 460GT: Use EMAC2+3 configuration */
 697 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 698 {                                                                                       \
 699 /* GPIO Core 0 */                                                                       \
 700 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0)      USB2HostD(0)    */      \
 701 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1)      USB2HostD(1)    */      \
 702 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2)      USB2HostD(2)    */      \
 703 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3)      USB2HostD(3)    */      \
 704 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4)      USB2HostD(4)    */      \
 705 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5)      USB2HostD(5)    */      \
 706 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6)      USB2HostD(6)    */      \
 707 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7)      USB2HostD(7)    */      \
 708 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0)      USB2OTGD(0)     */      \
 709 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1)      USB2OTGD(1)     */      \
 710 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)     USB2OTGD(2)     */      \
 711 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)     USB2OTGD(3)     */      \
 712 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)     USB2OTGD(4)     */      \
 713 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)     USB2OTGD(5)     */      \
 714 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)     USB2OTGD(6)     */      \
 715 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)     USB2OTGD(7)     */      \
 716 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER       USB2HostStop    */      \
 717 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD         USB2HostNext    */      \
 718 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER       USB2HostDir     */      \
 719 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN       USB2OTGStop     */      \
 720 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS        USB2OTGNext     */      \
 721 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV       USB2OTGDir      */      \
 722 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                          */      \
 723 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                          */      \
 724 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                          */      \
 725 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE                          */      \
 726 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE                          */      \
 727 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)                         */      \
 728 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)                         */      \
 729 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)                         */      \
 730 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0        DMAReq2         IRQ(7)*/ \
 731 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1        DMAAck2         IRQ(8)*/ \
 732 },                                                                                      \
 733 {                                                                                       \
 734 /* GPIO Core 1 */                                                                       \
 735 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2        EOT2/TC2        IRQ(9)*/ \
 736 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3        DMAReq3         IRQ(4)*/ \
 737 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 738 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 739 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3       UART3_SIN*/ \
 740 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EOT3/TC3        UART3_SOUT*/ \
 741 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 742 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 743 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                         */      \
 744 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                          */      \
 745 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                          */      \
 746 {GPIO1_BASE, GPIO_OUT, GPIO43_USE, GPIO_OUT_0},/* GPIO43 CS(3)          DMAReq1         IRQ(10)*/ \
 747 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)          DMAAck1         IRQ(11)*/ \
 748 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)          EOT/TC1         IRQ(12)*/ \
 749 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)     DMAReq0         IRQ(13)*/ \
 750 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)     DMAAck0         IRQ(14)*/ \
 751 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)     EOT/TC0         IRQ(15)*/ \
 752 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 753 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 754 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 755 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 756 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 757 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 758 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 759 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 760 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 761 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 762 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 763 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 764 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 765 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 766 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 767 }                                                                                       \
 768 }
 769 #endif
 770
 771 #endif  /* __CONFIG_H */