include/configs/canyonlands.h

   1 /*
   2  * (C) Copyright 2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /************************************************************************
   9  * canyonlands.h - configuration for Canyonlands (460EX)
  10  ***********************************************************************/
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include <linux/kconfig.h>
  15
  16 #define CONFIG_SYS_GENERIC_BOARD
  17
  18 /*-----------------------------------------------------------------------
  19  * High Level Configuration Options
  20  *----------------------------------------------------------------------*/
  21 /*
  22  * This config file is used for Canyonlands (460EX) Glacier (460GT)
  23  * and Arches dual (460GT)
  24  */
  25 #ifdef CONFIG_CANYONLANDS
  26 #define CONFIG_460EX                    /* Specific PPC460EX            */
  27 #define CONFIG_HOSTNAME         canyonlands
  28 #else
  29 #define CONFIG_460GT                    /* Specific PPC460GT            */
  30 #ifdef CONFIG_GLACIER
  31 #define CONFIG_HOSTNAME         glacier
  32 #else
  33 #define CONFIG_HOSTNAME         arches
  34 #define CONFIG_USE_NETDEV       eth1
  35 #define CONFIG_BD_NUM_CPUS      2
  36 #endif
  37 #endif
  38
  39 #define CONFIG_440
  40
  41 #ifndef CONFIG_SYS_TEXT_BASE
  42 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  43 #endif
  44
  45 /*
  46  * Include common defines/options for all AMCC eval boards
  47  */
  48 #include "amcc-common.h"
  49
  50 #define CONFIG_SYS_CLK_FREQ     66666667        /* external freq to pll */
  51
  52 #define CONFIG_BOARD_EARLY_INIT_F               /* Call board_early_init_f */
  53 #define CONFIG_BOARD_EARLY_INIT_R               /* Call board_early_init_r */
  54 #define CONFIG_MISC_INIT_R                      /* Call misc_init_r */
  55 #define CONFIG_BOARD_TYPES                      /* support board types */
  56
  57 /*-----------------------------------------------------------------------
  58  * Base addresses -- Note these are effective addresses where the
  59  * actual resources get mapped (not physical addresses)
  60  *----------------------------------------------------------------------*/
  61 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory    */
  62 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
  63 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
  64
  65 #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000      /* mapped PCIe memory   */
  66 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* smallest incr for PCIe port */
  67 #define CONFIG_SYS_PCIE_BASE            0xc4000000      /* PCIe UTL regs */
  68
  69 #define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
  70 #define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
  71 #define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
  72 #define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
  73
  74 /*
  75  * BCSR bits as defined in the Canyonlands board user manual.
  76  */
  77 #define BCSR_USBCTRL_OTG_RST    0x32
  78 #define BCSR_USBCTRL_HOST_RST   0x01
  79 #define BCSR_SELECT_PCIE        0x10
  80
  81 #define CONFIG_SYS_PCIE0_UTLBASE        0xc08010000ULL  /* 36bit physical addr  */
  82
  83 /* base address of inbound PCIe window */
  84 #define CONFIG_SYS_PCIE_INBOUND_BASE    0x000000000ULL  /* 36bit physical addr  */
  85
  86 /* EBC stuff */
  87 #if !defined(CONFIG_ARCHES)
  88 #define CONFIG_SYS_BCSR_BASE            0xE1000000
  89 #define CONFIG_SYS_FLASH_BASE           0xFC000000      /* later mapped to this addr */
  90 #define CONFIG_SYS_FLASH_SIZE           (64 << 20)
  91 #else
  92 #define CONFIG_SYS_FPGA_BASE            0xE1000000
  93 #define CONFIG_SYS_CPLD_ADDR            (CONFIG_SYS_FPGA_BASE + 0x00080000)
  94 #define CONFIG_SYS_CPLD_DATA            (CONFIG_SYS_FPGA_BASE + 0x00080002)
  95 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* later mapped to this addr  */
  96 #define CONFIG_SYS_FLASH_SIZE           (32 << 20)
  97 #endif
  98
  99 #define CONFIG_SYS_NAND_ADDR            0xE0000000
 100 #define CONFIG_SYS_BOOT_BASE_ADDR       0xFF000000      /* EBC Boot Space: 0xFF000000 */
 101 #define CONFIG_SYS_FLASH_BASE_PHYS_H    0x4
 102 #define CONFIG_SYS_FLASH_BASE_PHYS_L    0xCC000000
 103 #define CONFIG_SYS_FLASH_BASE_PHYS      (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) |    \
 104                                          (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
 105
 106 #define CONFIG_SYS_OCM_BASE             0xE3000000      /* OCM: 64k             */
 107 #define CONFIG_SYS_SRAM_BASE            0xE8000000      /* SRAM: 256k           */
 108 #define CONFIG_SYS_SRAM_SIZE            (256 << 10)
 109 #define CONFIG_SYS_LOCAL_CONF_REGS      0xEF000000
 110
 111 #define CONFIG_SYS_AHB_BASE             0xE2000000      /* internal AHB peripherals     */
 112
 113 /*-----------------------------------------------------------------------
 114  * Initial RAM & stack pointer (placed in OCM)
 115  *----------------------------------------------------------------------*/
 116 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
 117 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
 118 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 119 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 120
 121 /*-----------------------------------------------------------------------
 122  * Serial Port
 123  *----------------------------------------------------------------------*/
 124 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 125
 126 /*-----------------------------------------------------------------------
 127  * Environment
 128  *----------------------------------------------------------------------*/
 129 /*
 130  * Define here the location of the environment variables (FLASH).
 131  */
 132 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
 133 #define CONFIG_SYS_NOR_CS               0       /* NOR chip connected to CSx */
 134 #define CONFIG_SYS_NAND_CS              3       /* NAND chip connected to CSx */
 135
 136 /*-----------------------------------------------------------------------
 137  * FLASH related
 138  *----------------------------------------------------------------------*/
 139 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 140 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 141 #define CONFIG_SYS_FLASH_CFI_AMD_RESET  /* Use AMD (Spansion) reset cmd */
 142
 143 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 144 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 145 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 146
 147 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 148 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 149
 150 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 151 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 152
 153 #ifdef CONFIG_ENV_IS_IN_FLASH
 154 #define CONFIG_ENV_SECT_SIZE    0x20000         /* size of one complete sector  */
 155 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 156 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 157
 158 /* Address and size of Redundant Environment Sector     */
 159 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 160 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 161 #endif /* CONFIG_ENV_IS_IN_FLASH */
 162
 163 /*-----------------------------------------------------------------------
 164  * NAND-FLASH related
 165  *----------------------------------------------------------------------*/
 166 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 167 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 168 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips   */
 169
 170 /*------------------------------------------------------------------------------
 171  * DDR SDRAM
 172  *----------------------------------------------------------------------------*/
 173 #if !defined(CONFIG_ARCHES)
 174 /*
 175  * NAND booting U-Boot version uses a fixed initialization, since the whole
 176  * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
 177  * code.
 178  */
 179 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup     */
 180 #define SPD_EEPROM_ADDRESS      {0x50, 0x51}    /* SPD i2c spd addresses*/
 181 #define CONFIG_DDR_ECC                  /* with ECC support             */
 182 #define CONFIG_DDR_RQDC_FIXED   0x80000038 /* fixed value for RQDC      */
 183
 184 #else /* defined(CONFIG_ARCHES) */
 185
 186 #define CONFIG_AUTOCALIB        "silent\0"      /* default is non-verbose    */
 187
 188 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration   */
 189 #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
 190 #undef CONFIG_PPC4xx_DDR_METHOD_A
 191
 192 /* DDR1/2 SDRAM Device Control Register Data Values */
 193 /* Memory Queue */
 194 #define CONFIG_SYS_SDRAM_R0BAS          0x0000f000
 195 #define CONFIG_SYS_SDRAM_R1BAS          0x00000000
 196 #define CONFIG_SYS_SDRAM_R2BAS          0x00000000
 197 #define CONFIG_SYS_SDRAM_R3BAS          0x00000000
 198 #define CONFIG_SYS_SDRAM_PLBADDULL      0x00000000
 199 #define CONFIG_SYS_SDRAM_PLBADDUHB      0x00000008
 200 #define CONFIG_SYS_SDRAM_CONF1LL        0x00001080
 201 #define CONFIG_SYS_SDRAM_CONF1HB        0x00001080
 202 #define CONFIG_SYS_SDRAM_CONFPATHB      0x10a68000
 203
 204 /* SDRAM Controller */
 205 #define CONFIG_SYS_SDRAM0_MB0CF         0x00000701
 206 #define CONFIG_SYS_SDRAM0_MB1CF         0x00000000
 207 #define CONFIG_SYS_SDRAM0_MB2CF         0x00000000
 208 #define CONFIG_SYS_SDRAM0_MB3CF         0x00000000
 209 #define CONFIG_SYS_SDRAM0_MCOPT1        0x05322000
 210 #define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
 211 #define CONFIG_SYS_SDRAM0_MODT0         0x01000000
 212 #define CONFIG_SYS_SDRAM0_MODT1         0x00000000
 213 #define CONFIG_SYS_SDRAM0_MODT2         0x00000000
 214 #define CONFIG_SYS_SDRAM0_MODT3         0x00000000
 215 #define CONFIG_SYS_SDRAM0_CODT          0x00800021
 216 #define CONFIG_SYS_SDRAM0_RTR           0x06180000
 217 #define CONFIG_SYS_SDRAM0_INITPLR0      0xb5380000
 218 #define CONFIG_SYS_SDRAM0_INITPLR1      0x82100400
 219 #define CONFIG_SYS_SDRAM0_INITPLR2      0x80820000
 220 #define CONFIG_SYS_SDRAM0_INITPLR3      0x80830000
 221 #define CONFIG_SYS_SDRAM0_INITPLR4      0x80810040
 222 #define CONFIG_SYS_SDRAM0_INITPLR5      0x80800532
 223 #define CONFIG_SYS_SDRAM0_INITPLR6      0x82100400
 224 #define CONFIG_SYS_SDRAM0_INITPLR7      0x8a080000
 225 #define CONFIG_SYS_SDRAM0_INITPLR8      0x8a080000
 226 #define CONFIG_SYS_SDRAM0_INITPLR9      0x8a080000
 227 #define CONFIG_SYS_SDRAM0_INITPLR10     0x8a080000
 228 #define CONFIG_SYS_SDRAM0_INITPLR11     0x80000432
 229 #define CONFIG_SYS_SDRAM0_INITPLR12     0x808103c0
 230 #define CONFIG_SYS_SDRAM0_INITPLR13     0x80810040
 231 #define CONFIG_SYS_SDRAM0_INITPLR14     0x00000000
 232 #define CONFIG_SYS_SDRAM0_INITPLR15     0x00000000
 233 #define CONFIG_SYS_SDRAM0_RQDC          0x80000038
 234 #define CONFIG_SYS_SDRAM0_RFDC          0x00000257
 235 #define CONFIG_SYS_SDRAM0_RDCC          0x40000000
 236 #define CONFIG_SYS_SDRAM0_DLCR          0x03000091
 237 #define CONFIG_SYS_SDRAM0_CLKTR         0x40000000
 238 #define CONFIG_SYS_SDRAM0_WRDTR         0x82000823
 239 #define CONFIG_SYS_SDRAM0_SDTR1         0x80201000
 240 #define CONFIG_SYS_SDRAM0_SDTR2         0x42204243
 241 #define CONFIG_SYS_SDRAM0_SDTR3         0x090c0d1a
 242 #define CONFIG_SYS_SDRAM0_MMODE         0x00000432
 243 #define CONFIG_SYS_SDRAM0_MEMODE        0x00000004
 244 #endif  /* !defined(CONFIG_ARCHES) */
 245
 246 #define CONFIG_SYS_MBYTES_SDRAM 512     /* 512MB                        */
 247
 248 /*-----------------------------------------------------------------------
 249  * I2C
 250  *----------------------------------------------------------------------*/
 251 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 252
 253 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 254 #define CONFIG_SYS_I2C_EEPROM_ADDR              (0xa8>>1)
 255 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 256 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 257 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 258
 259 /* I2C bootstrap EEPROM */
 260 #if defined(CONFIG_ARCHES)
 261 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x54
 262 #else
 263 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
 264 #endif
 265 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 266 #define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 267
 268 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 269 #define CONFIG_DTT_LM75                         /* ON Semi's LM75       */
 270 #define CONFIG_DTT_AD7414                       /* use AD7414           */
 271 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 272 #define CONFIG_SYS_DTT_MAX_TEMP 70
 273 #define CONFIG_SYS_DTT_LOW_TEMP -30
 274 #define CONFIG_SYS_DTT_HYSTERESIS       3
 275
 276 #if defined(CONFIG_ARCHES)
 277 #define CONFIG_SYS_I2C_DTT_ADDR 0x4a            /* AD7414 I2C address   */
 278 #endif
 279
 280 #if !defined(CONFIG_ARCHES)
 281 /* RTC configuration */
 282 #define CONFIG_RTC_M41T62
 283 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 284 #endif
 285
 286 /*-----------------------------------------------------------------------
 287  * Ethernet
 288  *----------------------------------------------------------------------*/
 289 #define CONFIG_IBM_EMAC4_V4
 290
 291 #define CONFIG_HAS_ETH0
 292 #define CONFIG_HAS_ETH1
 293
 294 #if !defined(CONFIG_ARCHES)
 295 #define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 296 #define CONFIG_PHY1_ADDR        1
 297 /* Only Glacier (460GT) has 4 EMAC interfaces */
 298 #ifdef CONFIG_460GT
 299 #define CONFIG_PHY2_ADDR        2
 300 #define CONFIG_PHY3_ADDR        3
 301 #define CONFIG_HAS_ETH2
 302 #define CONFIG_HAS_ETH3
 303 #endif
 304
 305 #else /* defined(CONFIG_ARCHES) */
 306
 307 #define CONFIG_FIXED_PHY        0xFFFFFFFF
 308 #define CONFIG_PHY_ADDR         CONFIG_FIXED_PHY
 309 #define CONFIG_PHY1_ADDR        0
 310 #define CONFIG_PHY2_ADDR        1
 311 #define CONFIG_HAS_ETH2
 312
 313 #define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
 314                 {devnum, speed, duplex}
 315 #define CONFIG_SYS_FIXED_PHY_PORTS \
 316                 CONFIG_SYS_FIXED_PHY_PORT(0, 1000, FULL)
 317
 318 #define CONFIG_M88E1112_PHY
 319
 320 /*
 321  * For the GPCS_PHYx_ADDR PHY address, choose some PHY address not
 322  * used by CONFIG_PHYx_ADDR
 323  */
 324 #define CONFIG_GPCS_PHY_ADDR    0xA
 325 #define CONFIG_GPCS_PHY1_ADDR   0xB
 326 #define CONFIG_GPCS_PHY2_ADDR   0xC
 327 #endif  /* !defined(CONFIG_ARCHES) */
 328
 329 #define CONFIG_PHY_RESET                /* reset phy upon startup       */
 330 #define CONFIG_PHY_GIGE                 /* Include GbE speed/duplex detection */
 331 #define CONFIG_PHY_DYNAMIC_ANEG
 332
 333 /*-----------------------------------------------------------------------
 334  * USB-OHCI
 335  *----------------------------------------------------------------------*/
 336 /* Only Canyonlands (460EX) has USB */
 337 #ifdef CONFIG_460EX
 338 #define CONFIG_USB_OHCI_NEW
 339 #define CONFIG_USB_STORAGE
 340 #undef CONFIG_SYS_OHCI_BE_CONTROLLER            /* 460EX has little endian descriptors  */
 341 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register     */
 342 #define CONFIG_SYS_OHCI_USE_NPS         /* force NoPowerSwitching mode          */
 343 #define CONFIG_SYS_USB_OHCI_REGS_BASE   (CONFIG_SYS_AHB_BASE | 0xd0000)
 344 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 345 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 346 #define CONFIG_SYS_USB_OHCI_BOARD_INIT
 347 #endif
 348
 349 /*
 350  * Default environment variables
 351  */
 352 #if !defined(CONFIG_ARCHES)
 353 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 354         CONFIG_AMCC_DEF_ENV                                             \
 355         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 356         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 357         "kernel_addr=fc000000\0"                                        \
 358         "fdt_addr=fc1e0000\0"                                           \
 359         "ramdisk_addr=fc200000\0"                                       \
 360         "pciconfighost=1\0"                                             \
 361         "pcie_mode=RP:RP\0"                                             \
 362         ""
 363 #else /* defined(CONFIG_ARCHES) */
 364 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 365         CONFIG_AMCC_DEF_ENV                                             \
 366         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 367         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 368         "kernel_addr=fe000000\0"                                        \
 369         "fdt_addr=fe1e0000\0"                                           \
 370         "ramdisk_addr=fe200000\0"                                       \
 371         "pciconfighost=1\0"                                             \
 372         "pcie_mode=RP:RP\0"                                             \
 373         "ethprime=ppc_4xx_eth1\0"                                       \
 374         ""
 375 #endif  /* !defined(CONFIG_ARCHES) */
 376
 377 /*
 378  * Commands additional to the ones defined in amcc-common.h
 379  */
 380 #define CONFIG_CMD_CHIP_CONFIG
 381 #if defined(CONFIG_ARCHES)
 382 #define CONFIG_CMD_DTT
 383 #define CONFIG_CMD_PCI
 384 #define CONFIG_CMD_SDRAM
 385 #elif defined(CONFIG_CANYONLANDS)
 386 #define CONFIG_CMD_DATE
 387 #define CONFIG_CMD_DTT
 388 #define CONFIG_CMD_EXT2
 389 #define CONFIG_CMD_FAT
 390 #define CONFIG_CMD_NAND
 391 #define CONFIG_CMD_PCI
 392 #define CONFIG_CMD_SATA
 393 #define CONFIG_CMD_SDRAM
 394 #define CONFIG_CMD_SNTP
 395 #define CONFIG_CMD_USB
 396 #elif defined(CONFIG_GLACIER)
 397 #define CONFIG_CMD_DATE
 398 #define CONFIG_CMD_DTT
 399 #define CONFIG_CMD_NAND
 400 #define CONFIG_CMD_PCI
 401 #define CONFIG_CMD_SDRAM
 402 #define CONFIG_CMD_SNTP
 403 #else
 404 #error "board type not defined"
 405 #endif
 406
 407 /* Partitions */
 408 #define CONFIG_MAC_PARTITION
 409 #define CONFIG_DOS_PARTITION
 410 #define CONFIG_ISO_PARTITION
 411
 412 /*-----------------------------------------------------------------------
 413  * PCI stuff
 414  *----------------------------------------------------------------------*/
 415 /* General PCI */
 416 #define CONFIG_PCI                      /* include pci support          */
 417 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 418 #define CONFIG_PCI_PNP                  /* do pci plug-and-play   */
 419 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 420 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 421
 422 /* Board-specific PCI */
 423 #define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
 424 #undef  CONFIG_SYS_PCI_MASTER_INIT
 425
 426 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM                          */
 427 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever                     */
 428
 429 #ifdef CONFIG_460GT
 430 #if defined(CONFIG_ARCHES)
 431 /*-----------------------------------------------------------------------
 432  * RapidIO I/O and Registers
 433  *----------------------------------------------------------------------*/
 434 #define CONFIG_RAPIDIO
 435 #define CONFIG_SYS_460GT_SRIO_ERRATA_1
 436
 437 #define SRGPL0_REG_BAR          0x0000000DAA000000ull   /*  16MB */
 438 #define SRGPL0_CFG_BAR          0x0000000DAB000000ull   /*  16MB */
 439 #define SRGPL0_MNT_BAR          0x0000000DAC000000ull   /*  16MB */
 440 #define SRGPL0_MSG_BAR          0x0000000DAD000000ull   /*  16MB */
 441 #define SRGPL0_OUT_BAR          0x0000000DB0000000ull   /* 256MB */
 442
 443 #define CONFIG_SYS_SRGPL0_REG_BAR       0xAA000000              /*  16MB */
 444 #define CONFIG_SYS_SRGPL0_CFG_BAR       0xAB000000              /*  16MB */
 445 #define CONFIG_SYS_SRGPL0_MNT_BAR       0xAC000000              /*  16MB */
 446 #define CONFIG_SYS_SRGPL0_MSG_BAR       0xAD000000              /*  16MB */
 447
 448 #define CONFIG_SYS_I2ODMA_BASE          0xCF000000
 449 #define CONFIG_SYS_I2ODMA_PHYS_ADDR     0x0000000400100000ull
 450
 451 #define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
 452 #undef CONFIG_PPC4XX_RAPIDIO_DEBUG
 453 #undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
 454 #define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
 455 #undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
 456 #endif /* CONFIG_ARCHES */
 457 #endif /* CONFIG_460GT */
 458
 459 /*
 460  * SATA driver setup
 461  */
 462 #ifdef CONFIG_CMD_SATA
 463 #define CONFIG_SATA_DWC
 464 #define CONFIG_LIBATA
 465 #define SATA_BASE_ADDR          0xe20d1000      /* PPC460EX SATA Base Address */
 466 #define SATA_DMA_REG_ADDR       0xe20d0800      /* PPC460EX SATA Base Address */
 467 #define CONFIG_SYS_SATA_MAX_DEVICE      1       /* SATA MAX DEVICE */
 468 /* Convert sectorsize to wordsize */
 469 #define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
 470 #endif
 471
 472 /*-----------------------------------------------------------------------
 473  * External Bus Controller (EBC) Setup
 474  *----------------------------------------------------------------------*/
 475
 476 /*
 477  * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
 478  * boot EBC mapping only supports a maximum of 16MBytes
 479  * (4.ff00.0000 - 4.ffff.ffff).
 480  * To solve this problem, the FLASH has to get remapped to another
 481  * EBC address which accepts bigger regions:
 482  *
 483  * 0xfc00.0000 -> 4.cc00.0000
 484  *
 485  * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), it will be
 486  * remapped to:
 487  *
 488  * 0xfe00.0000 -> 4.ce00.0000
 489  */
 490
 491 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
 492 #define CONFIG_SYS_EBC_PB0AP            0x10055e00
 493 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
 494
 495 #if !defined(CONFIG_ARCHES)
 496 /* Memory Bank 3 (NAND-FLASH) initialization                                            */
 497 #define CONFIG_SYS_EBC_PB3AP            0x018003c0
 498 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
 499 #endif
 500
 501 #if !defined(CONFIG_ARCHES)
 502 /* Memory Bank 2 (CPLD) initialization                                          */
 503 #define CONFIG_SYS_EBC_PB2AP            0x00804240
 504 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
 505
 506 #else /* defined(CONFIG_ARCHES) */
 507
 508 /* Memory Bank 1 (FPGA) initialization  */
 509 #define CONFIG_SYS_EBC_PB1AP            0x7f8ffe80
 510 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
 511 #endif  /* !defined(CONFIG_ARCHES) */
 512
 513 #define CONFIG_SYS_EBC_CFG              0xbfc00000
 514
 515 /*
 516  * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
 517  * pin multiplexing correctly
 518  */
 519 #if defined(CONFIG_ARCHES)
 520 #define GPIO43_USE              GPIO_SEL        /* On Arches this pin is used as GPIO */
 521 #else
 522 #define GPIO43_USE              GPIO_ALT1       /* On Glacier this pin is used as ALT1 -> PerCS3 */
 523 #endif
 524
 525 /*
 526  * PPC4xx GPIO Configuration
 527  */
 528 #ifdef CONFIG_460EX
 529 /* 460EX: Use USB configuration */
 530 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 531 {                                                                                       \
 532 /* GPIO Core 0 */                                                                       \
 533 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0)      USB2HostD(0)    */      \
 534 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1)      USB2HostD(1)    */      \
 535 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2)      USB2HostD(2)    */      \
 536 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3)      USB2HostD(3)    */      \
 537 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4)      USB2HostD(4)    */      \
 538 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5)      USB2HostD(5)    */      \
 539 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6)      USB2HostD(6)    */      \
 540 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7)      USB2HostD(7)    */      \
 541 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0)      USB2OTGD(0)     */      \
 542 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1)      USB2OTGD(1)     */      \
 543 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)     USB2OTGD(2)     */      \
 544 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)     USB2OTGD(3)     */      \
 545 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)     USB2OTGD(4)     */      \
 546 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)     USB2OTGD(5)     */      \
 547 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)     USB2OTGD(6)     */      \
 548 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)     USB2OTGD(7)     */      \
 549 {GPIO0_BASE, GPIO_IN , GPIO_SEL,  GPIO_OUT_0}, /* GPIO16 GMC1TxER       USB2HostStop    */      \
 550 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD         USB2HostNext    */      \
 551 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER       USB2HostDir     */      \
 552 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO19 GMC1TxEN       USB2OTGStop     */      \
 553 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS        USB2OTGNext     */      \
 554 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV       USB2OTGDir      */      \
 555 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                          */      \
 556 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                          */      \
 557 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                          */      \
 558 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE                          */      \
 559 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE                          */      \
 560 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)                         */      \
 561 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)                         */      \
 562 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)                         */      \
 563 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0        DMAReq2         IRQ(7)*/ \
 564 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1        DMAAck2         IRQ(8)*/ \
 565 },                                                                                      \
 566 {                                                                                       \
 567 /* GPIO Core 1 */                                                                       \
 568 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2        EOT2/TC2        IRQ(9)*/ \
 569 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3        DMAReq3         IRQ(4)*/ \
 570 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 571 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 572 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3       UART3_SIN*/ \
 573 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EOT3/TC3        UART3_SOUT*/ \
 574 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 575 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 576 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                         */      \
 577 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                          */      \
 578 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                          */      \
 579 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)          DMAReq1         IRQ(10)*/ \
 580 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)          DMAAck1         IRQ(11)*/ \
 581 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)          EOT/TC1         IRQ(12)*/ \
 582 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)     DMAReq0         IRQ(13)*/ \
 583 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)     DMAAck0         IRQ(14)*/ \
 584 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)     EOT/TC0         IRQ(15)*/ \
 585 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 586 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 587 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 588 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 589 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 590 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 591 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 592 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 593 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 594 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 595 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 596 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 597 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 598 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 599 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 600 }                                                                                       \
 601 }
 602 #else
 603 /* 460GT: Use EMAC2+3 configuration */
 604 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 605 {                                                                                       \
 606 /* GPIO Core 0 */                                                                       \
 607 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0)      USB2HostD(0)    */      \
 608 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1)      USB2HostD(1)    */      \
 609 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2)      USB2HostD(2)    */      \
 610 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3)      USB2HostD(3)    */      \
 611 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4)      USB2HostD(4)    */      \
 612 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5)      USB2HostD(5)    */      \
 613 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6)      USB2HostD(6)    */      \
 614 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7)      USB2HostD(7)    */      \
 615 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0)      USB2OTGD(0)     */      \
 616 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1)      USB2OTGD(1)     */      \
 617 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)     USB2OTGD(2)     */      \
 618 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)     USB2OTGD(3)     */      \
 619 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)     USB2OTGD(4)     */      \
 620 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)     USB2OTGD(5)     */      \
 621 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)     USB2OTGD(6)     */      \
 622 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)     USB2OTGD(7)     */      \
 623 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER       USB2HostStop    */      \
 624 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD         USB2HostNext    */      \
 625 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER       USB2HostDir     */      \
 626 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN       USB2OTGStop     */      \
 627 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS        USB2OTGNext     */      \
 628 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV       USB2OTGDir      */      \
 629 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                          */      \
 630 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                          */      \
 631 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                          */      \
 632 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE                          */      \
 633 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE                          */      \
 634 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)                         */      \
 635 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)                         */      \
 636 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)                         */      \
 637 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0        DMAReq2         IRQ(7)*/ \
 638 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1        DMAAck2         IRQ(8)*/ \
 639 },                                                                                      \
 640 {                                                                                       \
 641 /* GPIO Core 1 */                                                                       \
 642 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2        EOT2/TC2        IRQ(9)*/ \
 643 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3        DMAReq3         IRQ(4)*/ \
 644 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 645 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 646 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3       UART3_SIN*/ \
 647 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EOT3/TC3        UART3_SOUT*/ \
 648 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 649 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 650 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                         */      \
 651 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                          */      \
 652 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                          */      \
 653 {GPIO1_BASE, GPIO_OUT, GPIO43_USE, GPIO_OUT_0},/* GPIO43 CS(3)          DMAReq1         IRQ(10)*/ \
 654 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)          DMAAck1         IRQ(11)*/ \
 655 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)          EOT/TC1         IRQ(12)*/ \
 656 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)     DMAReq0         IRQ(13)*/ \
 657 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)     DMAAck0         IRQ(14)*/ \
 658 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)     EOT/TC0         IRQ(15)*/ \
 659 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 660 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 661 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 662 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 663 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 664 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 665 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 666 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 667 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 668 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 669 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 670 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 671 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 672 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 673 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 674 }                                                                                       \
 675 }
 676 #endif
 677
 678 #endif  /* __CONFIG_H */