include/configs/canyonlands.h

   1 /*
   2  * (C) Copyright 2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 /************************************************************************
  22  * canyonlands.h - configuration for Canyonlands (460EX)
  23  ***********************************************************************/
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*-----------------------------------------------------------------------
  28  * High Level Configuration Options
  29  *----------------------------------------------------------------------*/
  30 /*
  31  * This config file is used for Canyonlands (460EX) Glacier (460GT)
  32  * and Arches dual (460GT)
  33  */
  34 #ifdef CONFIG_CANYONLANDS
  35 #define CONFIG_460EX            1       /* Specific PPC460EX            */
  36 #define CONFIG_HOSTNAME         canyonlands
  37 #else
  38 #define CONFIG_460GT            1       /* Specific PPC460GT            */
  39 #ifdef CONFIG_GLACIER
  40 #define CONFIG_HOSTNAME         glacier
  41 #else
  42 #define CONFIG_HOSTNAME         arches
  43 #define CONFIG_USE_NETDEV       eth1
  44 #define CONFIG_BD_NUM_CPUS      2
  45 #endif
  46 #endif
  47
  48 #define CONFIG_440              1
  49 #define CONFIG_4xx              1       /* ... PPC4xx family */
  50
  51 /*
  52  * Include common defines/options for all AMCC eval boards
  53  */
  54 #include "amcc-common.h"
  55
  56 #define CONFIG_SYS_CLK_FREQ     66666667        /* external freq to pll */
  57
  58 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_early_init_f */
  59 #define CONFIG_BOARD_EARLY_INIT_R       1       /* Call board_early_init_r */
  60 #define CONFIG_MISC_INIT_R              1       /* Call misc_init_r */
  61 #define CONFIG_BOARD_TYPES              1       /* support board types */
  62
  63 /*-----------------------------------------------------------------------
  64  * Base addresses -- Note these are effective addresses where the
  65  * actual resources get mapped (not physical addresses)
  66  *----------------------------------------------------------------------*/
  67 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory    */
  68 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
  69 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
  70
  71 #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000      /* mapped PCIe memory   */
  72 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* smallest incr for PCIe port */
  73 #define CONFIG_SYS_PCIE_BASE            0xc4000000      /* PCIe UTL regs */
  74
  75 #define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
  76 #define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
  77 #define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
  78 #define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
  79
  80 #define CONFIG_SYS_PCIE0_UTLBASE        0xc08010000ULL  /* 36bit physical addr  */
  81
  82 /* base address of inbound PCIe window */
  83 #define CONFIG_SYS_PCIE_INBOUND_BASE    0x000000000ULL  /* 36bit physical addr  */
  84
  85 /* EBC stuff */
  86 #if !defined(CONFIG_ARCHES)
  87 #define CONFIG_SYS_BCSR_BASE            0xE1000000
  88 #define CONFIG_SYS_FLASH_BASE           0xFC000000      /* later mapped to this addr */
  89 #define CONFIG_SYS_FLASH_SIZE           (64 << 20)
  90 #else
  91 #define CONFIG_SYS_FPGA_BASE            0xE1000000
  92 #define CONFIG_SYS_CPLD_ADDR            (CONFIG_SYS_FPGA_BASE + 0x00080000)
  93 #define CONFIG_SYS_CPLD_DATA            (CONFIG_SYS_FPGA_BASE + 0x00080002)
  94 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* later mapped to this addr  */
  95 #define CONFIG_SYS_FLASH_SIZE           (32 << 20)
  96 #endif
  97
  98 #define CONFIG_SYS_NAND_ADDR            0xE0000000
  99 #define CONFIG_SYS_BOOT_BASE_ADDR       0xFF000000      /* EBC Boot Space: 0xFF000000 */
 100 #define CONFIG_SYS_FLASH_BASE_PHYS_H    0x4
 101 #define CONFIG_SYS_FLASH_BASE_PHYS_L    0xCC000000
 102 #define CONFIG_SYS_FLASH_BASE_PHYS      (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) |    \
 103                                          (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
 104
 105 #define CONFIG_SYS_OCM_BASE             0xE3000000      /* OCM: 64k             */
 106 #define CONFIG_SYS_SRAM_BASE            0xE8000000      /* SRAM: 256k           */
 107 #define CONFIG_SYS_LOCAL_CONF_REGS      0xEF000000
 108
 109 #define CONFIG_SYS_PERIPHERAL_BASE      0xEF600000      /* internal peripherals */
 110
 111 #define CONFIG_SYS_AHB_BASE             0xE2000000      /* internal AHB peripherals     */
 112
 113 /*-----------------------------------------------------------------------
 114  * Initial RAM & stack pointer (placed in OCM)
 115  *----------------------------------------------------------------------*/
 116 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
 117 #define CONFIG_SYS_INIT_RAM_END (4 << 10)
 118 #define CONFIG_SYS_GBL_DATA_SIZE        256             /* num bytes initial data */
 119 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 120 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 121
 122 /*-----------------------------------------------------------------------
 123  * Serial Port
 124  *----------------------------------------------------------------------*/
 125 #undef CONFIG_UART1_CONSOLE     /* define this if you want console on UART1 */
 126
 127 /*-----------------------------------------------------------------------
 128  * Environment
 129  *----------------------------------------------------------------------*/
 130 /*
 131  * Define here the location of the environment variables (FLASH).
 132  */
 133 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 134 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
 135 #define CONFIG_SYS_NOR_CS               0       /* NOR chip connected to CSx */
 136 #define CONFIG_SYS_NAND_CS              3       /* NAND chip connected to CSx */
 137 #else
 138 #define CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars  */
 139 #define CONFIG_SYS_NOR_CS               3       /* NOR chip connected to CSx */
 140 #define CONFIG_SYS_NAND_CS              0       /* NAND chip connected to CSx */
 141 #define CONFIG_ENV_IS_EMBEDDED  1       /* use embedded environment */
 142 #endif
 143
 144 /*
 145  * IPL (Initial Program Loader, integrated inside CPU)
 146  * Will load first 4k from NAND (SPL) into cache and execute it from there.
 147  *
 148  * SPL (Secondary Program Loader)
 149  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 150  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 151  * controller and the NAND controller so that the special U-Boot image can be
 152  * loaded from NAND to SDRAM.
 153  *
 154  * NUB (NAND U-Boot)
 155  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 156  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 157  *
 158  * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 159  * set up. While still running from cache, I experienced problems accessing
 160  * the NAND controller. sr - 2006-08-25
 161  *
 162  * This is the first official implementation of booting from 2k page sized
 163  * NAND devices (e.g. Micron 29F2G08AA 256Mbit * 8)
 164  */
 165 #define CONFIG_SYS_NAND_BOOT_SPL_SRC    0xfffff000      /* SPL location               */
 166 #define CONFIG_SYS_NAND_BOOT_SPL_SIZE   (4 << 10)       /* SPL size                   */
 167 #define CONFIG_SYS_NAND_BOOT_SPL_DST    (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here  */
 168 #define CONFIG_SYS_NAND_U_BOOT_DST      0x01000000      /* Load NUB to this addr      */
 169 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST      /* Start NUB from     */
 170                                                         /*   this addr        */
 171 #define CONFIG_SYS_NAND_BOOT_SPL_DELTA  (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 172
 173 /*
 174  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 175  */
 176 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)     /* Offset to RAM U-Boot image */
 177 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (1 << 20)       /* Size of RAM U-Boot image   */
 178
 179 /*
 180  * Now the NAND chip has to be defined (no autodetection used!)
 181  */
 182 #define CONFIG_SYS_NAND_PAGE_SIZE       (2 << 10)       /* NAND chip page size        */
 183 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)     /* NAND chip block size       */
 184 #define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)
 185                                                 /* NAND chip page count       */
 186 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0               /* Location of bad block marker*/
 187 #define CONFIG_SYS_NAND_5_ADDR_CYCLE                    /* Fifth addr used (<=128MB)  */
 188
 189 #define CONFIG_SYS_NAND_ECCSIZE 256
 190 #define CONFIG_SYS_NAND_ECCBYTES        3
 191 #define CONFIG_SYS_NAND_ECCSTEPS        (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
 192 #define CONFIG_SYS_NAND_OOBSIZE 64
 193 #define CONFIG_SYS_NAND_ECCTOTAL        (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
 194 #define CONFIG_SYS_NAND_ECCPOS          {40, 41, 42, 43, 44, 45, 46, 47, \
 195                                  48, 49, 50, 51, 52, 53, 54, 55, \
 196                                  56, 57, 58, 59, 60, 61, 62, 63}
 197
 198 #ifdef CONFIG_ENV_IS_IN_NAND
 199 /*
 200  * For NAND booting the environment is embedded in the U-Boot image. Please take
 201  * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
 202  */
 203 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 204 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 205 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 206 #endif
 207
 208 /*-----------------------------------------------------------------------
 209  * FLASH related
 210  *----------------------------------------------------------------------*/
 211 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 212 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 213 #define CONFIG_SYS_FLASH_CFI_AMD_RESET  1       /* Use AMD (Spansion) reset cmd */
 214
 215 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 216 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 217 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 218
 219 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 220 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 221
 222 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 223 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 224
 225 #ifdef CONFIG_ENV_IS_IN_FLASH
 226 #define CONFIG_ENV_SECT_SIZE    0x20000         /* size of one complete sector  */
 227 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 228 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 229
 230 /* Address and size of Redundant Environment Sector     */
 231 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 232 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 233 #endif /* CONFIG_ENV_IS_IN_FLASH */
 234
 235 /*-----------------------------------------------------------------------
 236  * NAND-FLASH related
 237  *----------------------------------------------------------------------*/
 238 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 239 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 240 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips   */
 241
 242 /*------------------------------------------------------------------------------
 243  * DDR SDRAM
 244  *----------------------------------------------------------------------------*/
 245 #if !defined(CONFIG_NAND_U_BOOT)
 246 #if !defined(CONFIG_ARCHES)
 247 /*
 248  * NAND booting U-Boot version uses a fixed initialization, since the whole
 249  * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
 250  * code.
 251  */
 252 #define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
 253 #define SPD_EEPROM_ADDRESS      {0x50, 0x51}    /* SPD i2c spd addresses*/
 254 #define CONFIG_DDR_ECC          1       /* with ECC support             */
 255 #define CONFIG_DDR_RQDC_FIXED   0x80000038 /* fixed value for RQDC      */
 256
 257 #else /* defined(CONFIG_ARCHES) */
 258
 259 #define CONFIG_AUTOCALIB        "silent\0"      /* default is non-verbose    */
 260
 261 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration   */
 262 #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
 263 #undef CONFIG_PPC4xx_DDR_METHOD_A
 264
 265 /* DDR1/2 SDRAM Device Control Register Data Values */
 266 /* Memory Queue */
 267 #define CONFIG_SYS_SDRAM_R0BAS          0x0000f000
 268 #define CONFIG_SYS_SDRAM_R1BAS          0x00000000
 269 #define CONFIG_SYS_SDRAM_R2BAS          0x00000000
 270 #define CONFIG_SYS_SDRAM_R3BAS          0x00000000
 271 #define CONFIG_SYS_SDRAM_PLBADDULL      0x00000000
 272 #define CONFIG_SYS_SDRAM_PLBADDUHB      0x00000008
 273 #define CONFIG_SYS_SDRAM_CONF1LL        0x00001080
 274 #define CONFIG_SYS_SDRAM_CONF1HB        0x00001080
 275 #define CONFIG_SYS_SDRAM_CONFPATHB      0x10a68000
 276
 277 /* SDRAM Controller */
 278 #define CONFIG_SYS_SDRAM0_MB0CF         0x00000701
 279 #define CONFIG_SYS_SDRAM0_MB1CF         0x00000000
 280 #define CONFIG_SYS_SDRAM0_MB2CF         0x00000000
 281 #define CONFIG_SYS_SDRAM0_MB3CF         0x00000000
 282 #define CONFIG_SYS_SDRAM0_MCOPT1        0x05322000
 283 #define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
 284 #define CONFIG_SYS_SDRAM0_MODT0         0x01000000
 285 #define CONFIG_SYS_SDRAM0_MODT1         0x00000000
 286 #define CONFIG_SYS_SDRAM0_MODT2         0x00000000
 287 #define CONFIG_SYS_SDRAM0_MODT3         0x00000000
 288 #define CONFIG_SYS_SDRAM0_CODT          0x00800021
 289 #define CONFIG_SYS_SDRAM0_RTR           0x06180000
 290 #define CONFIG_SYS_SDRAM0_INITPLR0      0xb5380000
 291 #define CONFIG_SYS_SDRAM0_INITPLR1      0x82100400
 292 #define CONFIG_SYS_SDRAM0_INITPLR2      0x80820000
 293 #define CONFIG_SYS_SDRAM0_INITPLR3      0x80830000
 294 #define CONFIG_SYS_SDRAM0_INITPLR4      0x80810040
 295 #define CONFIG_SYS_SDRAM0_INITPLR5      0x80800532
 296 #define CONFIG_SYS_SDRAM0_INITPLR6      0x82100400
 297 #define CONFIG_SYS_SDRAM0_INITPLR7      0x8a080000
 298 #define CONFIG_SYS_SDRAM0_INITPLR8      0x8a080000
 299 #define CONFIG_SYS_SDRAM0_INITPLR9      0x8a080000
 300 #define CONFIG_SYS_SDRAM0_INITPLR10     0x8a080000
 301 #define CONFIG_SYS_SDRAM0_INITPLR11     0x80000432
 302 #define CONFIG_SYS_SDRAM0_INITPLR12     0x808103c0
 303 #define CONFIG_SYS_SDRAM0_INITPLR13     0x80810040
 304 #define CONFIG_SYS_SDRAM0_INITPLR14     0x00000000
 305 #define CONFIG_SYS_SDRAM0_INITPLR15     0x00000000
 306 #define CONFIG_SYS_SDRAM0_RQDC          0x80000038
 307 #define CONFIG_SYS_SDRAM0_RFDC          0x00000257
 308 #define CONFIG_SYS_SDRAM0_RDCC          0x40000000
 309 #define CONFIG_SYS_SDRAM0_DLCR          0x03000091
 310 #define CONFIG_SYS_SDRAM0_CLKTR         0x40000000
 311 #define CONFIG_SYS_SDRAM0_WRDTR         0x82000823
 312 #define CONFIG_SYS_SDRAM0_SDTR1         0x80201000
 313 #define CONFIG_SYS_SDRAM0_SDTR2         0x42204243
 314 #define CONFIG_SYS_SDRAM0_SDTR3         0x090c0d1a
 315 #define CONFIG_SYS_SDRAM0_MMODE         0x00000432
 316 #define CONFIG_SYS_SDRAM0_MEMODE        0x00000004
 317 #endif  /* !defined(CONFIG_ARCHES) */
 318 #endif  /* !defined(CONFIG_NAND_U_BOOT) */
 319
 320 #define CONFIG_SYS_MBYTES_SDRAM 512     /* 512MB                        */
 321
 322 /*-----------------------------------------------------------------------
 323  * I2C
 324  *----------------------------------------------------------------------*/
 325 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed                    */
 326
 327 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 328 #define CONFIG_SYS_I2C_EEPROM_ADDR              (0xa8>>1)
 329 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 330 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 331 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 332
 333 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 334 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 335 #define CONFIG_DTT_AD7414       1               /* use AD7414           */
 336 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 337 #define CONFIG_SYS_DTT_MAX_TEMP 70
 338 #define CONFIG_SYS_DTT_LOW_TEMP -30
 339 #define CONFIG_SYS_DTT_HYSTERESIS       3
 340
 341 #if defined(CONFIG_ARCHES)
 342 #define CONFIG_SYS_I2C_DTT_ADDR 0x4a            /* AD7414 I2C address   */
 343 #endif
 344
 345 #if !defined(CONFIG_ARCHES)
 346 /* RTC configuration */
 347 #define CONFIG_RTC_M41T62       1
 348 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 349 #endif
 350
 351 /*-----------------------------------------------------------------------
 352  * Ethernet
 353  *----------------------------------------------------------------------*/
 354 #define CONFIG_IBM_EMAC4_V4     1
 355
 356 #define CONFIG_HAS_ETH0
 357 #define CONFIG_HAS_ETH1
 358
 359 #if !defined(CONFIG_ARCHES)
 360 #define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 361 #define CONFIG_PHY1_ADDR        1
 362 /* Only Glacier (460GT) has 4 EMAC interfaces */
 363 #ifdef CONFIG_460GT
 364 #define CONFIG_PHY2_ADDR        2
 365 #define CONFIG_PHY3_ADDR        3
 366 #define CONFIG_HAS_ETH2
 367 #define CONFIG_HAS_ETH3
 368 #endif
 369
 370 #else /* defined(CONFIG_ARCHES) */
 371
 372 #define CONFIG_FIXED_PHY        0xFFFFFFFF
 373 #define CONFIG_PHY_ADDR         CONFIG_FIXED_PHY
 374 #define CONFIG_PHY1_ADDR        0
 375 #define CONFIG_PHY2_ADDR        1
 376 #define CONFIG_HAS_ETH2
 377
 378 #define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
 379                 {devnum, speed, duplex}
 380 #define CONFIG_SYS_FIXED_PHY_PORTS \
 381                 CONFIG_SYS_FIXED_PHY_PORT(0, 1000, FULL)
 382
 383 #define CONFIG_M88E1112_PHY
 384
 385 /*
 386  * For the GPCS_PHYx_ADDR PHY address, choose some PHY address not
 387  * used by CONFIG_PHYx_ADDR
 388  */
 389 #define CONFIG_GPCS_PHY_ADDR    0xA
 390 #define CONFIG_GPCS_PHY1_ADDR   0xB
 391 #define CONFIG_GPCS_PHY2_ADDR   0xC
 392 #endif  /* !defined(CONFIG_ARCHES) */
 393
 394 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 395 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 396 #define CONFIG_PHY_DYNAMIC_ANEG 1
 397
 398 /*-----------------------------------------------------------------------
 399  * USB-OHCI
 400  *----------------------------------------------------------------------*/
 401 /* Only Canyonlands (460EX) has USB */
 402 #ifdef CONFIG_460EX
 403 #define CONFIG_USB_OHCI_NEW
 404 #define CONFIG_USB_STORAGE
 405 #undef CONFIG_SYS_OHCI_BE_CONTROLLER            /* 460EX has little endian descriptors  */
 406 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register     */
 407 #define CONFIG_SYS_OHCI_USE_NPS         /* force NoPowerSwitching mode          */
 408 #define CONFIG_SYS_USB_OHCI_REGS_BASE   (CONFIG_SYS_AHB_BASE | 0xd0000)
 409 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 410 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 411 #endif
 412
 413 /*
 414  * Default environment variables
 415  */
 416 #if !defined(CONFIG_ARCHES)
 417 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 418         CONFIG_AMCC_DEF_ENV                                             \
 419         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 420         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 421         CONFIG_AMCC_DEF_ENV_NAND_UPD                                    \
 422         "kernel_addr=fc000000\0"                                        \
 423         "fdt_addr=fc1e0000\0"                                           \
 424         "ramdisk_addr=fc200000\0"                                       \
 425         "pciconfighost=1\0"                                             \
 426         "pcie_mode=RP:RP\0"                                             \
 427         ""
 428 #else /* defined(CONFIG_ARCHES) */
 429 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 430         CONFIG_AMCC_DEF_ENV                                             \
 431         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 432         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 433         "kernel_addr=fe000000\0"                                        \
 434         "fdt_addr=fe1e0000\0"                                           \
 435         "ramdisk_addr=fe200000\0"                                       \
 436         "pciconfighost=1\0"                                             \
 437         "pcie_mode=RP:RP\0"                                             \
 438         "ethprime=ppc_4xx_eth1\0"                                       \
 439         ""
 440 #endif  /* !defined(CONFIG_ARCHES) */
 441
 442 /*
 443  * Commands additional to the ones defined in amcc-common.h
 444  */
 445 #if defined(CONFIG_ARCHES)
 446 #define CONFIG_CMD_DTT
 447 #define CONFIG_CMD_PCI
 448 #define CONFIG_CMD_SDRAM
 449 #elif defined(CONFIG_CANYONLANDS)
 450 #define CONFIG_CMD_DATE
 451 #define CONFIG_CMD_DTT
 452 #define CONFIG_CMD_EXT2
 453 #define CONFIG_CMD_FAT
 454 #define CONFIG_CMD_NAND
 455 #define CONFIG_CMD_PCI
 456 #define CONFIG_CMD_SATA
 457 #define CONFIG_CMD_SDRAM
 458 #define CONFIG_CMD_SNTP
 459 #define CONFIG_CMD_USB
 460 #elif defined(CONFIG_GLACIER)
 461 #define CONFIG_CMD_DATE
 462 #define CONFIG_CMD_DTT
 463 #define CONFIG_CMD_NAND
 464 #define CONFIG_CMD_PCI
 465 #define CONFIG_CMD_SDRAM
 466 #define CONFIG_CMD_SNTP
 467 #else
 468 #error "board type not defined"
 469 #endif
 470
 471 /* Partitions */
 472 #define CONFIG_MAC_PARTITION
 473 #define CONFIG_DOS_PARTITION
 474 #define CONFIG_ISO_PARTITION
 475
 476 /*-----------------------------------------------------------------------
 477  * PCI stuff
 478  *----------------------------------------------------------------------*/
 479 /* General PCI */
 480 #define CONFIG_PCI                      /* include pci support          */
 481 #define CONFIG_PCI_PNP                  /* do pci plug-and-play   */
 482 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 483 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 484
 485 /* Board-specific PCI */
 486 #define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
 487 #undef  CONFIG_SYS_PCI_MASTER_INIT
 488
 489 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM                          */
 490 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever                     */
 491
 492 #ifdef CONFIG_460GT
 493 #if defined(CONFIG_ARCHES)
 494 /*-----------------------------------------------------------------------
 495  * RapidIO I/O and Registers
 496  *----------------------------------------------------------------------*/
 497 #define CONFIG_RAPIDIO
 498 #define CONFIG_SYS_460GT_SRIO_ERRATA_1
 499
 500 #define SRGPL0_REG_BAR          0x0000000DAA000000ull   /*  16MB */
 501 #define SRGPL0_CFG_BAR          0x0000000DAB000000ull   /*  16MB */
 502 #define SRGPL0_MNT_BAR          0x0000000DAC000000ull   /*  16MB */
 503 #define SRGPL0_MSG_BAR          0x0000000DAD000000ull   /*  16MB */
 504 #define SRGPL0_OUT_BAR          0x0000000DB0000000ull   /* 256MB */
 505
 506 #define CONFIG_SYS_SRGPL0_REG_BAR       0xAA000000              /*  16MB */
 507 #define CONFIG_SYS_SRGPL0_CFG_BAR       0xAB000000              /*  16MB */
 508 #define CONFIG_SYS_SRGPL0_MNT_BAR       0xAC000000              /*  16MB */
 509 #define CONFIG_SYS_SRGPL0_MSG_BAR       0xAD000000              /*  16MB */
 510
 511 #define CONFIG_SYS_I2ODMA_BASE          0xCF000000
 512 #define CONFIG_SYS_I2ODMA_PHYS_ADDR     0x0000000400100000ull
 513
 514 #define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
 515 #undef CONFIG_PPC4XX_RAPIDIO_DEBUG
 516 #undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
 517 #define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
 518 #undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
 519 #endif /* CONFIG_ARCHES */
 520 #endif /* CONFIG_460GT */
 521
 522 /*
 523  * SATA driver setup
 524  */
 525 #ifdef CONFIG_CMD_SATA
 526 #define CONFIG_SATA_DWC
 527 #define CONFIG_LIBATA
 528 #define SATA_BASE_ADDR          0xe20d1000      /* PPC460EX SATA Base Address */
 529 #define SATA_DMA_REG_ADDR       0xe20d0800      /* PPC460EX SATA Base Address */
 530 #define CONFIG_SYS_SATA_MAX_DEVICE      1       /* SATA MAX DEVICE */
 531 /* Convert sectorsize to wordsize */
 532 #define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
 533 #endif
 534
 535 /*-----------------------------------------------------------------------
 536  * External Bus Controller (EBC) Setup
 537  *----------------------------------------------------------------------*/
 538
 539 /*
 540  * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
 541  * boot EBC mapping only supports a maximum of 16MBytes
 542  * (4.ff00.0000 - 4.ffff.ffff).
 543  * To solve this problem, the FLASH has to get remapped to another
 544  * EBC address which accepts bigger regions:
 545  *
 546  * 0xfc00.0000 -> 4.cc00.0000
 547  *
 548  * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), it will be
 549  * remapped to:
 550  *
 551  * 0xfe00.0000 -> 4.ce00.0000
 552  */
 553
 554 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 555 /* Memory Bank 3 (NOR-FLASH) initialization                                     */
 556 #define CONFIG_SYS_EBC_PB3AP            0x10055e00
 557 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
 558
 559 /* Memory Bank 0 (NAND-FLASH) initialization                                            */
 560 #define CONFIG_SYS_EBC_PB0AP            0x018003c0
 561 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
 562 #else
 563 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
 564 #define CONFIG_SYS_EBC_PB0AP            0x10055e00
 565 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
 566
 567 #if !defined(CONFIG_ARCHES)
 568 /* Memory Bank 3 (NAND-FLASH) initialization                                            */
 569 #define CONFIG_SYS_EBC_PB3AP            0x018003c0
 570 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
 571 #endif
 572 #endif  /*defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
 573
 574 #if !defined(CONFIG_ARCHES)
 575 /* Memory Bank 2 (CPLD) initialization                                          */
 576 #define CONFIG_SYS_EBC_PB2AP            0x00804240
 577 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
 578
 579 #else /* defined(CONFIG_ARCHES) */
 580
 581 /* Memory Bank 1 (FPGA) initialization  */
 582 #define CONFIG_SYS_EBC_PB1AP            0x7f8ffe80
 583 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
 584 #endif  /* !defined(CONFIG_ARCHES) */
 585
 586 #define CONFIG_SYS_EBC_CFG              0xB8400000              /*  EBC0_CFG */
 587
 588 /*
 589  * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
 590  * pin multiplexing correctly
 591  */
 592 #if defined(CONFIG_ARCHES)
 593 #define GPIO43_USE              GPIO_SEL        /* On Arches this pin is used as GPIO */
 594 #else
 595 #define GPIO43_USE              GPIO_ALT1       /* On Glacier this pin is used as ALT1 -> PerCS3 */
 596 #endif
 597
 598 /*
 599  * PPC4xx GPIO Configuration
 600  */
 601 #ifdef CONFIG_460EX
 602 /* 460EX: Use USB configuration */
 603 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 604 {                                                                                       \
 605 /* GPIO Core 0 */                                                                       \
 606 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0)      USB2HostD(0)    */      \
 607 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1)      USB2HostD(1)    */      \
 608 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2)      USB2HostD(2)    */      \
 609 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3)      USB2HostD(3)    */      \
 610 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4)      USB2HostD(4)    */      \
 611 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5)      USB2HostD(5)    */      \
 612 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6)      USB2HostD(6)    */      \
 613 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7)      USB2HostD(7)    */      \
 614 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0)      USB2OTGD(0)     */      \
 615 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1)      USB2OTGD(1)     */      \
 616 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)     USB2OTGD(2)     */      \
 617 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)     USB2OTGD(3)     */      \
 618 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)     USB2OTGD(4)     */      \
 619 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)     USB2OTGD(5)     */      \
 620 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)     USB2OTGD(6)     */      \
 621 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)     USB2OTGD(7)     */      \
 622 {GPIO0_BASE, GPIO_IN , GPIO_SEL,  GPIO_OUT_0}, /* GPIO16 GMC1TxER       USB2HostStop    */      \
 623 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD         USB2HostNext    */      \
 624 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER       USB2HostDir     */      \
 625 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO19 GMC1TxEN       USB2OTGStop     */      \
 626 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS        USB2OTGNext     */      \
 627 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV       USB2OTGDir      */      \
 628 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                          */      \
 629 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                          */      \
 630 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                          */      \
 631 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE                          */      \
 632 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE                          */      \
 633 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)                         */      \
 634 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)                         */      \
 635 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)                         */      \
 636 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0        DMAReq2         IRQ(7)*/ \
 637 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1        DMAAck2         IRQ(8)*/ \
 638 },                                                                                      \
 639 {                                                                                       \
 640 /* GPIO Core 1 */                                                                       \
 641 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2        EOT2/TC2        IRQ(9)*/ \
 642 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3        DMAReq3         IRQ(4)*/ \
 643 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 644 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 645 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3       UART3_SIN*/ \
 646 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EOT3/TC3        UART3_SOUT*/ \
 647 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 648 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 649 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                         */      \
 650 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                          */      \
 651 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                          */      \
 652 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)          DMAReq1         IRQ(10)*/ \
 653 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)          DMAAck1         IRQ(11)*/ \
 654 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)          EOT/TC1         IRQ(12)*/ \
 655 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)     DMAReq0         IRQ(13)*/ \
 656 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)     DMAAck0         IRQ(14)*/ \
 657 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)     EOT/TC0         IRQ(15)*/ \
 658 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 659 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 660 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 661 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 662 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 663 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 664 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 665 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 666 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 667 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 668 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 669 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 670 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 671 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 672 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 673 }                                                                                       \
 674 }
 675 #else
 676 /* 460GT: Use EMAC2+3 configuration */
 677 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 678 {                                                                                       \
 679 /* GPIO Core 0 */                                                                       \
 680 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0)      USB2HostD(0)    */      \
 681 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1)      USB2HostD(1)    */      \
 682 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2)      USB2HostD(2)    */      \
 683 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3)      USB2HostD(3)    */      \
 684 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4)      USB2HostD(4)    */      \
 685 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5)      USB2HostD(5)    */      \
 686 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6)      USB2HostD(6)    */      \
 687 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7)      USB2HostD(7)    */      \
 688 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0)      USB2OTGD(0)     */      \
 689 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1)      USB2OTGD(1)     */      \
 690 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)     USB2OTGD(2)     */      \
 691 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)     USB2OTGD(3)     */      \
 692 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)     USB2OTGD(4)     */      \
 693 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)     USB2OTGD(5)     */      \
 694 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)     USB2OTGD(6)     */      \
 695 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)     USB2OTGD(7)     */      \
 696 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER       USB2HostStop    */      \
 697 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD         USB2HostNext    */      \
 698 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER       USB2HostDir     */      \
 699 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN       USB2OTGStop     */      \
 700 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS        USB2OTGNext     */      \
 701 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV       USB2OTGDir      */      \
 702 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                          */      \
 703 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                          */      \
 704 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                          */      \
 705 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE                          */      \
 706 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE                          */      \
 707 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)                         */      \
 708 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)                         */      \
 709 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)                         */      \
 710 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0        DMAReq2         IRQ(7)*/ \
 711 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1        DMAAck2         IRQ(8)*/ \
 712 },                                                                                      \
 713 {                                                                                       \
 714 /* GPIO Core 1 */                                                                       \
 715 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2        EOT2/TC2        IRQ(9)*/ \
 716 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3        DMAReq3         IRQ(4)*/ \
 717 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 718 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 719 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3       UART3_SIN*/ \
 720 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EOT3/TC3        UART3_SOUT*/ \
 721 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 722 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 723 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                         */      \
 724 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                          */      \
 725 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                          */      \
 726 {GPIO1_BASE, GPIO_OUT, GPIO43_USE, GPIO_OUT_0},/* GPIO43 CS(3)          DMAReq1         IRQ(10)*/ \
 727 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)          DMAAck1         IRQ(11)*/ \
 728 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)          EOT/TC1         IRQ(12)*/ \
 729 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)     DMAReq0         IRQ(13)*/ \
 730 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)     DMAAck0         IRQ(14)*/ \
 731 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)     EOT/TC0         IRQ(15)*/ \
 732 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 733 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 734 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 735 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 736 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 737 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 738 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 739 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 740 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 741 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 742 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 743 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 744 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 745 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 746 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 747 }                                                                                       \
 748 }
 749 #endif
 750
 751 #endif  /* __CONFIG_H */