include/configs/cm_t3517.h

   1 /*
   2  * (C) Copyright 2013 CompuLab, Ltd.
   3  * Author: Igor Grinberg <grinberg@compulab.co.il>
   4  *
   5  * Configuration settings for the CompuLab CM-T3517 board
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * High Level Configuration Options
  15  */
  16 #define CONFIG_CM_T3517 /* working with CM-T3517 */
  17
  18 #define CONFIG_SYS_TEXT_BASE    0x80008000
  19
  20 /*
  21  * This is needed for the DMA stuff.
  22  * Although the default iss 64, we still define it
  23  * to be on the safe side once the default is changed.
  24  */
  25
  26 #define CONFIG_EMIF4    /* The chip has EMIF4 controller */
  27
  28 #include <asm/arch/cpu.h>               /* get chip and board defs */
  29 #include <asm/arch/omap.h>
  30
  31 #define CONFIG_MACH_TYPE                MACH_TYPE_CM_T3517
  32
  33 /* Clock Defines */
  34 #define V_OSCK                  26000000        /* Clock output from T2 */
  35 #define V_SCLK                  (V_OSCK >> 1)
  36
  37 #define CONFIG_MISC_INIT_R
  38
  39 /*
  40  * The early kernel mapping on ARM currently only maps from the base of DRAM
  41  * to the end of the kernel image.  The kernel is loaded at DRAM base + 0x8000.
  42  * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
  43  * so that leaves DRAM base to DRAM base + 0x4000 available.
  44  */
  45 #define CONFIG_SYS_BOOTMAPSZ            0x4000
  46
  47 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  48 #define CONFIG_SETUP_MEMORY_TAGS
  49 #define CONFIG_INITRD_TAG
  50 #define CONFIG_REVISION_TAG
  51 #define CONFIG_SERIAL_TAG
  52
  53 /*
  54  * Size of malloc() pool
  55  */
  56 #define CONFIG_ENV_SIZE         (128 << 10)     /* 128 KiB */
  57 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + (128 << 10))
  58
  59 /*
  60  * Hardware drivers
  61  */
  62
  63 /*
  64  * NS16550 Configuration
  65  */
  66 #define CONFIG_SYS_NS16550_SERIAL
  67 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  68 #define CONFIG_SYS_NS16550_CLK          48000000        /* 48MHz (APLL96/2) */
  69
  70 /*
  71  * select serial console configuration
  72  */
  73 #define CONFIG_CONS_INDEX               3
  74 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  75 #define CONFIG_SERIAL3                  3       /* UART3 */
  76
  77 /* allow to overwrite serial and ethaddr */
  78 #define CONFIG_ENV_OVERWRITE
  79 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  80                                         115200}
  81
  82 #define CONFIG_OMAP_GPIO
  83
  84 /* USB */
  85 #define CONFIG_USB_MUSB_AM35X
  86
  87 #ifndef CONFIG_USB_MUSB_AM35X
  88 #define CONFIG_USB_OMAP3
  89 #define CONFIG_USB_EHCI
  90 #define CONFIG_USB_EHCI_OMAP
  91 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
  92 #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
  93 #else /* !CONFIG_USB_MUSB_AM35X */
  94 #define CONFIG_USB_MUSB_PIO_ONLY
  95 #endif /* CONFIG_USB_MUSB_AM35X */
  96
  97 /* commands to include */
  98 #define CONFIG_CMD_MTDPARTS     /* Enable MTD parts commands */
  99 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 100 #define CONFIG_MTD_PARTITIONS
 101 #define MTDIDS_DEFAULT          "nand0=nand"
 102 #define MTDPARTS_DEFAULT        "mtdparts=nand:512k(x-loader),"\
 103                                 "1920k(u-boot),256k(u-boot-env),"\
 104                                 "4m(kernel),-(fs)"
 105
 106 #define CONFIG_CMD_NAND         /* NAND support                 */
 107
 108 #define CONFIG_SYS_I2C
 109 #define CONFIG_SYS_OMAP24_I2C_SPEED     400000
 110 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
 111 #define CONFIG_SYS_I2C_OMAP34XX
 112 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 113 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 114 #define CONFIG_SYS_I2C_EEPROM_BUS       0
 115 #define CONFIG_I2C_MULTI_BUS
 116
 117 /*
 118  * Board NAND Info.
 119  */
 120 #define CONFIG_NAND_OMAP_GPMC
 121 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 122                                                         /* to access nand */
 123 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 124                                                         /* to access nand at */
 125                                                         /* CS0 */
 126 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 127                                                         /* devices */
 128
 129 /* Environment information */
 130 #define CONFIG_EXTRA_ENV_SETTINGS \
 131         "loadaddr=0x82000000\0" \
 132         "baudrate=115200\0" \
 133         "console=ttyO2,115200n8\0" \
 134         "netretry=yes\0" \
 135         "mpurate=auto\0" \
 136         "vram=12M\0" \
 137         "dvimode=1024x768MR-16@60\0" \
 138         "defaultdisplay=dvi\0" \
 139         "mmcdev=0\0" \
 140         "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
 141         "mmcrootfstype=ext4\0" \
 142         "nandroot=/dev/mtdblock4 rw\0" \
 143         "nandrootfstype=ubifs\0" \
 144         "mmcargs=setenv bootargs console=${console} " \
 145                 "mpurate=${mpurate} " \
 146                 "vram=${vram} " \
 147                 "omapfb.mode=dvi:${dvimode} " \
 148                 "omapdss.def_disp=${defaultdisplay} " \
 149                 "root=${mmcroot} " \
 150                 "rootfstype=${mmcrootfstype}\0" \
 151         "nandargs=setenv bootargs console=${console} " \
 152                 "mpurate=${mpurate} " \
 153                 "vram=${vram} " \
 154                 "omapfb.mode=dvi:${dvimode} " \
 155                 "omapdss.def_disp=${defaultdisplay} " \
 156                 "root=${nandroot} " \
 157                 "rootfstype=${nandrootfstype}\0" \
 158         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 159         "bootscript=echo Running bootscript from mmc ...; " \
 160                 "source ${loadaddr}\0" \
 161         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 162         "mmcboot=echo Booting from mmc ...; " \
 163                 "run mmcargs; " \
 164                 "bootm ${loadaddr}\0" \
 165         "nandboot=echo Booting from nand ...; " \
 166                 "run nandargs; " \
 167                 "nand read ${loadaddr} 2a0000 400000; " \
 168                 "bootm ${loadaddr}\0" \
 169
 170 #define CONFIG_BOOTCOMMAND \
 171         "mmc dev ${mmcdev}; if mmc rescan; then " \
 172                 "if run loadbootscript; then " \
 173                         "run bootscript; " \
 174                 "else " \
 175                         "if run loaduimage; then " \
 176                                 "run mmcboot; " \
 177                         "else run nandboot; " \
 178                         "fi; " \
 179                 "fi; " \
 180         "else run nandboot; fi"
 181
 182 /*
 183  * Miscellaneous configurable options
 184  */
 185 #define CONFIG_AUTO_COMPLETE
 186 #define CONFIG_CMDLINE_EDITING
 187 #define CONFIG_TIMESTAMP
 188 #define CONFIG_SYS_AUTOLOAD             "no"
 189 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 190 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 191 /* Print Buffer Size */
 192 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 193                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 194 #define CONFIG_SYS_MAXARGS              32      /* max number of command args */
 195 /* Boot Argument Buffer Size */
 196 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 197
 198 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0 + 0x02000000)
 199
 200 /*
 201  * AM3517 has 12 GP timers, they can be driven by the system clock
 202  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 203  * This rate is divided by a local divisor.
 204  */
 205 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 206 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 207 #define CONFIG_SYS_HZ                   1000
 208
 209 /*-----------------------------------------------------------------------
 210  * Physical Memory Map
 211  */
 212 #define CONFIG_NR_DRAM_BANKS    1       /* CM-T3517 DRAM is only on CS0 */
 213 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 214 #define CONFIG_SYS_CS0_SIZE             (256 << 20)
 215
 216 /*-----------------------------------------------------------------------
 217  * FLASH and environment organization
 218  */
 219
 220 /* **** PISMO SUPPORT *** */
 221 /* Monitor at start of flash */
 222 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 223 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 224
 225 #define CONFIG_ENV_IS_IN_NAND
 226 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 227 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 228 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 229
 230 #if defined(CONFIG_CMD_NET)
 231 #define CONFIG_DRIVER_TI_EMAC
 232 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
 233 #define CONFIG_MII
 234 #define CONFIG_SMC911X
 235 #define CONFIG_SMC911X_32_BIT
 236 #define CONFIG_SMC911X_BASE     (0x2C000000 + (16 << 20))
 237 #define CONFIG_ARP_TIMEOUT              200UL
 238 #define CONFIG_NET_RETRY_COUNT          5
 239 #endif /* CONFIG_CMD_NET */
 240
 241 /* additions for new relocation code, must be added to all boards */
 242 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 243 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 244 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 245 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR +     \
 246                                          CONFIG_SYS_INIT_RAM_SIZE -     \
 247                                          GENERATED_GBL_DATA_SIZE)
 248
 249 /* Status LED */
 250 #define GREEN_LED_GPIO                  186 /* CM-T3517 Green LED is GPIO186 */
 251
 252 /* GPIO banks */
 253 #ifdef CONFIG_LED_STATUS
 254 #define CONFIG_OMAP3_GPIO_6     /* GPIO186 is in GPIO bank 6  */
 255 #endif
 256
 257 /* Display Configuration */
 258 #define CONFIG_OMAP3_GPIO_2
 259 #define CONFIG_OMAP3_GPIO_5
 260 #define CONFIG_VIDEO_OMAP3
 261 #define LCD_BPP         LCD_COLOR16
 262
 263 #define CONFIG_SPLASH_SCREEN
 264 #define CONFIG_SPLASHIMAGE_GUARD
 265 #define CONFIG_BMP_16BPP
 266 #define CONFIG_SCF0403_LCD
 267
 268 #define CONFIG_OMAP3_SPI
 269
 270 /* EEPROM */
 271 #define CONFIG_CMD_EEPROM
 272 #define CONFIG_ENV_EEPROM_IS_ON_I2C
 273 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 274 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 275 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 276 #define CONFIG_SYS_EEPROM_SIZE                  256
 277
 278 #define CONFIG_CMD_EEPROM_LAYOUT
 279 #define CONFIG_EEPROM_LAYOUT_HELP_STRING "v1, v2, v3"
 280
 281 #endif /* __CONFIG_H */