include/configs/cogent_mpc8260.h

   1 /*
   2  * (C) Copyright 2000
   3  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Config header file for Cogent platform using an MPC8xx CPU module
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU       */
  37 #define CONFIG_COGENT           1       /* using Cogent Modular Architecture */
  38 #define CONFIG_CPM2             1       /* Has a CPM2 */
  39
  40 #define CONFIG_SYS_TEXT_BASE    0xfff00000
  41
  42 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()            */
  43 #define CONFIG_MISC_INIT_R              /* Use misc_init_r()            */
  44
  45 /* Cogent Modular Architecture options */
  46 #define CONFIG_CMA282           1       /* ...on a CMA282 CPU module    */
  47 #define CONFIG_CMA111           1       /* ...on a CMA111 motherboard   */
  48
  49 /*
  50  * select serial console configuration
  51  *
  52  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  53  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  54  * for SCC).
  55  *
  56  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  57  * defined elsewhere (for example, on the cogent platform, there are serial
  58  * ports on the motherboard which are used for the serial console - see
  59  * cogent/cma101/serial.[ch]).
  60  */
  61 #define CONFIG_CONS_ON_SMC              /* define if console on SMC */
  62 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
  63 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  64 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  65 #undef  CONFIG_CONS_USE_EXTC            /* SMC/SCC use ext clock not brg_clk */
  66 #define CONFIG_CONS_EXTC_RATE   3686400 /* SMC/SCC ext clk rate in Hz */
  67 #define CONFIG_CONS_EXTC_PINSEL 0       /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
  68
  69 /*
  70  * select ethernet configuration
  71  *
  72  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  73  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  74  * for FCC)
  75  *
  76  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  77  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  78  */
  79 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
  80 #undef  CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
  81 #define CONFIG_ETHER_NONE               /* define if ether on something else */
  82 #define CONFIG_ETHER_INDEX      1       /* which channel for ether      */
  83
  84 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
  85 #define CONFIG_8260_CLKIN       66666666        /* in Hz */
  86
  87 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  88 #define CONFIG_BAUDRATE         230400
  89 #else
  90 #define CONFIG_BAUDRATE         9600
  91 #endif
  92
  93
  94 /*
  95  * BOOTP options
  96  */
  97 #define CONFIG_BOOTP_BOOTFILESIZE
  98 #define CONFIG_BOOTP_BOOTPATH
  99 #define CONFIG_BOOTP_GATEWAY
 100 #define CONFIG_BOOTP_HOSTNAME
 101
 102
 103 /*
 104  * Command line configuration.
 105  */
 106 #include <config_cmd_default.h>
 107
 108 #define CONFIG_CMD_KGDB
 109
 110 #undef CONFIG_CMD_NET
 111 #undef CONFIG_CMD_NFS
 112
 113 #ifdef DEBUG
 114 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
 115 #else
 116 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 117 #endif
 118 #define CONFIG_BOOTCOMMAND      "bootm 04080000 04200000" /* autoboot command*/
 119
 120 #define CONFIG_BOOTARGS         "root=/dev/ram rw"
 121
 122 #if defined(CONFIG_CMD_KGDB)
 123 #define CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 124 #undef  CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 125 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 126 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 127 #define CONFIG_KGDB_USE_EXTC            /* SMC/SCC use ext clock not brg_clk */
 128 #define CONFIG_KGDB_EXTC_RATE   3686400 /* serial ext clk rate in Hz */
 129 #define CONFIG_KGDB_EXTC_PINSEL 0       /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
 130 # if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC)
 131 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port at */
 132 # else
 133 #define CONFIG_KGDB_BAUDRATE    9600    /* speed to run kgdb serial port at */
 134 # endif
 135 #endif
 136
 137 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 138
 139 /*
 140  * Miscellaneous configurable options
 141  */
 142 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 143 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 144 #if defined(CONFIG_CMD_KGDB)
 145 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 146 #else
 147 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 148 #endif
 149 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 150 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 151 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 152
 153 #define CONFIG_SYS_MEMTEST_START        0x00400000      /* memtest works on     */
 154 #define CONFIG_SYS_MEMTEST_END          0x01c00000      /* 4 ... 28 MB in DRAM  */
 155
 156 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 157
 158 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 159
 160 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 161
 162 /*
 163  * Low Level Configuration Settings
 164  * (address mappings, register initial values, etc.)
 165  * You should know what you are doing if you make changes here.
 166  */
 167
 168 /*-----------------------------------------------------------------------
 169  * Low Level Cogent settings
 170  * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
 171  * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
 172  * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
 173  * (second 2 for CMA120 only)
 174  */
 175 #define CONFIG_SYS_CMA_MB_BASE          0x00000000      /* base of m/b address space */
 176
 177 #include <configs/cogent_common.h>
 178
 179 #ifdef CONFIG_CONS_NONE
 180 #define CONFIG_SYS_CMA_CONS_SERIAL      /* use Cogent motherboard serial for console */
 181 #endif
 182 #define CONFIG_SYS_CMA_LCD_HEARTBEAT    /* define for sec rotator in lcd corner */
 183 #define CONFIG_SHOW_ACTIVITY
 184
 185 #if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
 186 /*
 187  * flash exists on the motherboard
 188  * set these four according to TOP dipsw:
 189  * TOP on  => ..._FLLOW_...     (boot EPROM space is high so FLASH is low )
 190  * TOP off => ..._FLHIGH_...    (boot EPROM space is low  so FLASH is high)
 191  */
 192 #define CMA_MB_FLASH_EXEC_BASE  CMA_MB_FLLOW_EXEC_BASE
 193 #define CMA_MB_FLASH_EXEC_SIZE  CMA_MB_FLLOW_EXEC_SIZE
 194 #define CMA_MB_FLASH_RDWR_BASE  CMA_MB_FLLOW_RDWR_BASE
 195 #define CMA_MB_FLASH_RDWR_SIZE  CMA_MB_FLLOW_RDWR_SIZE
 196 #endif
 197 #define CMA_MB_FLASH_BASE       CMA_MB_FLASH_EXEC_BASE
 198 #define CMA_MB_FLASH_SIZE       CMA_MB_FLASH_EXEC_SIZE
 199
 200 /*-----------------------------------------------------------------------
 201  * Hard Reset Configuration Words
 202  *
 203  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 204  * defines for the various registers affected by the HRCW e.g. changing
 205  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 206  */
 207 #define CONFIG_SYS_HRCW_MASTER  (HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\
 208                          HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101)
 209 /* no slaves so just duplicate the master hrcw */
 210 #define CONFIG_SYS_HRCW_SLAVE1  CONFIG_SYS_HRCW_MASTER
 211 #define CONFIG_SYS_HRCW_SLAVE2  CONFIG_SYS_HRCW_MASTER
 212 #define CONFIG_SYS_HRCW_SLAVE3  CONFIG_SYS_HRCW_MASTER
 213 #define CONFIG_SYS_HRCW_SLAVE4  CONFIG_SYS_HRCW_MASTER
 214 #define CONFIG_SYS_HRCW_SLAVE5  CONFIG_SYS_HRCW_MASTER
 215 #define CONFIG_SYS_HRCW_SLAVE6  CONFIG_SYS_HRCW_MASTER
 216 #define CONFIG_SYS_HRCW_SLAVE7  CONFIG_SYS_HRCW_MASTER
 217
 218 /*-----------------------------------------------------------------------
 219  * Internal Memory Mapped Register
 220  */
 221 #define CONFIG_SYS_IMMR         0xF0000000
 222
 223 /*-----------------------------------------------------------------------
 224  * Definitions for initial stack pointer and data area (in DPRAM)
 225  */
 226 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 227 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM   */
 228 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 229 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 230
 231 /*-----------------------------------------------------------------------
 232  * Start addresses for the final memory configuration
 233  * (Set up by the startup code)
 234  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 235  */
 236 #define CONFIG_SYS_SDRAM_BASE           CMA_MB_RAM_BASE
 237 #ifdef CONFIG_CMA302
 238 #define CONFIG_SYS_FLASH_BASE           CMA_MB_SLOT2_BASE       /* cma302 in slot 2 */
 239 #else
 240 #define CONFIG_SYS_FLASH_BASE           CMA_MB_FLASH_BASE       /* flash on m/b */
 241 #endif
 242 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 243 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 244 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 245
 246 /*
 247  * For booting Linux, the board info and command line data
 248  * have to be in the first 8 MB of memory, since this is
 249  * the maximum mapped by the Linux kernel during initialization.
 250  */
 251 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Mem map for Linux*/
 252
 253 /*-----------------------------------------------------------------------
 254  * FLASH organization
 255  */
 256 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of memory banks      */
 257 #define CONFIG_SYS_MAX_FLASH_SECT       67      /* max num of sects on one chip */
 258
 259 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Flash Erase Timeout (in ms)  */
 260 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 261
 262 #define CONFIG_ENV_IS_IN_FLASH  1
 263 #define CONFIG_ENV_ADDR         CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
 264 #ifdef CONFIG_CMA302
 265 #define CONFIG_ENV_SIZE         0x1000  /* Total Size of Environment Sector */
 266 #define CONFIG_ENV_SECT_SIZE    (512*1024) /* see README - env sect real size */
 267 #else
 268 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector */
 269 #endif
 270
 271 /*-----------------------------------------------------------------------
 272  * Cache Configuration
 273  */
 274 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPU              */
 275 #if defined(CONFIG_CMD_KGDB)
 276 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value*/
 277 #endif
 278
 279 /*-----------------------------------------------------------------------
 280  * HIDx - Hardware Implementation-dependent Registers                    2-11
 281  *-----------------------------------------------------------------------
 282  * HID0 also contains cache control - initially enable both caches and
 283  * invalidate contents, then the final state leaves only the instruction
 284  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 285  * but Soft reset does not.
 286  *
 287  * HID1 has only read-only information - nothing to set.
 288  */
 289 #define CONFIG_SYS_HID0_INIT    (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 290                                 HID0_IFEM|HID0_ABE)
 291 #define CONFIG_SYS_HID0_FINAL   (HID0_ICE|HID0_IFEM|HID0_ABE)
 292 #define CONFIG_SYS_HID2 0
 293
 294 /*-----------------------------------------------------------------------
 295  * RMR - Reset Mode Register                                     5-5
 296  *-----------------------------------------------------------------------
 297  * turn on Checkstop Reset Enable
 298  */
 299 #define CONFIG_SYS_RMR          RMR_CSRE
 300
 301 /*-----------------------------------------------------------------------
 302  * BCR - Bus Configuration                                       4-25
 303  *-----------------------------------------------------------------------
 304  */
 305 #define CONFIG_SYS_BCR          BCR_EBM
 306
 307 /*-----------------------------------------------------------------------
 308  * SIUMCR - SIU Module Configuration                             4-31
 309  *-----------------------------------------------------------------------
 310  */
 311 #define CONFIG_SYS_SIUMCR       (SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)
 312
 313 /*-----------------------------------------------------------------------
 314  * SYPCR - System Protection Control                             4-35
 315  * SYPCR can only be written once after reset!
 316  *-----------------------------------------------------------------------
 317  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 318  */
 319 #if defined(CONFIG_WATCHDOG)
 320 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 321                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 322 #else
 323 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 324                          SYPCR_SWRI|SYPCR_SWP)
 325 #endif /* CONFIG_WATCHDOG */
 326
 327 /*-----------------------------------------------------------------------
 328  * TMCNTSC - Time Counter Status and Control                     4-40
 329  *-----------------------------------------------------------------------
 330  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 331  * and enable Time Counter
 332  */
 333 #define CONFIG_SYS_TMCNTSC      (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 334
 335 /*-----------------------------------------------------------------------
 336  * PISCR - Periodic Interrupt Status and Control                 4-42
 337  *-----------------------------------------------------------------------
 338  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 339  * Periodic timer
 340  */
 341 #define CONFIG_SYS_PISCR        (PISCR_PS|PISCR_PTF|PISCR_PTE)
 342
 343 /*-----------------------------------------------------------------------
 344  * SCCR - System Clock Control                                   9-8
 345  *-----------------------------------------------------------------------
 346  * Ensure DFBRG is Divide by 16
 347  */
 348 #define CONFIG_SYS_SCCR (SCCR_DFBRG01)
 349
 350 /*-----------------------------------------------------------------------
 351  * RCCR - RISC Controller Configuration                         13-7
 352  *-----------------------------------------------------------------------
 353  */
 354 #define CONFIG_SYS_RCCR 0
 355
 356 #if defined(CONFIG_CMA282)
 357
 358 /*
 359  * Init Memory Controller:
 360  *
 361  * According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM
 362  * and CS2 for (optional) local bus RAM on the CPU module.
 363  *
 364  * Note the motherboard address space (256 Mbyte in size) is connected
 365  * to the 60x Bus and is located starting at address 0. The Hard Reset
 366  * Configuration Word should put the 60x Bus into External Bus Mode, since
 367  * we dont set up any memory controller maps for it (see BCR[EBM], 4-26).
 368  *
 369  * (the *_SIZE vars must be a power of 2)
 370  */
 371
 372 #define CONFIG_SYS_CMA_CS0_BASE CONFIG_SYS_TEXT_BASE    /* EPROM */
 373 #define CONFIG_SYS_CMA_CS0_SIZE (1 << 20)
 374 #if 0
 375 #define CONFIG_SYS_CMA_CS2_BASE 0x10000000      /* Local Bus SDRAM */
 376 #define CONFIG_SYS_CMA_CS2_SIZE (16 << 20)
 377 #endif
 378
 379 /*
 380  * CS0 maps the EPROM on the cpu module
 381  * Set it for 10 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
 382  *
 383  * Note: We must have already transferred control to the final location
 384  * of the EPROM before these are used, because when BR0/OR0 are set, the
 385  * mirror of the eprom at any other addresses will disappear.
 386  */
 387
 388 /* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
 389 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
 390 /* mask size CONFIG_SYS_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
 391 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_CMA_CS0_SIZE)|\
 392                                 ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
 393
 394 /*
 395  * CS2 enables the Local Bus SDRAM on the CPU Module
 396  *
 397  * Will leave this unset for the moment, because a) my CPU module has no
 398  * SDRAM installed (it is optional); and b) it will require programming
 399  * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
 400  * if you can't test it.
 401  */
 402
 403 #if 0
 404 /* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, ??? */
 405 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
 406 /* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, ??? */
 407 #define CONFIG_SYS_OR2_PRELIM   ((~(CONFIG_SYS_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
 408 #endif
 409
 410 #endif
 411 #endif  /* __CONFIG_H */