include/configs/corenet_ds.h

   1 /*
   2  * Copyright 2009-2012 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * Corenet DS style board configuration file
  25  */
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 #include "../board/freescale/common/ics307_clk.h"
  30
  31 #ifdef CONFIG_RAMBOOT_PBL
  32 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  33 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  34 #endif
  35
  36 #ifdef CONFIG_SRIOBOOT_SLAVE
  37 /* Set 1M boot space */
  38 #define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  39 #define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \
  40                 (0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR)
  41 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  42 #define CONFIG_SYS_NO_FLASH
  43 #endif
  44
  45 /* High Level Configuration Options */
  46 #define CONFIG_BOOKE
  47 #define CONFIG_E500                     /* BOOKE e500 family */
  48 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  49 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  50 #define CONFIG_MPC85xx                  /* MPC85xx/PQ3 platform */
  51 #define CONFIG_FSL_CORENET              /* Freescale CoreNet platform */
  52 #define CONFIG_MP                       /* support multiple processors */
  53
  54 #ifndef CONFIG_SYS_TEXT_BASE
  55 #define CONFIG_SYS_TEXT_BASE    0xeff80000
  56 #endif
  57
  58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  59 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  60 #endif
  61
  62 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  63 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  64 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
  65 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  66 #define CONFIG_PCIE1                    /* PCIE controler 1 */
  67 #define CONFIG_PCIE2                    /* PCIE controler 2 */
  68 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  69 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  70
  71 #define CONFIG_SYS_SRIO
  72 #define CONFIG_SRIO1                    /* SRIO port 1 */
  73 #define CONFIG_SRIO2                    /* SRIO port 2 */
  74
  75 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  76
  77 #define CONFIG_ENV_OVERWRITE
  78
  79 #ifdef CONFIG_SYS_NO_FLASH
  80 #ifndef CONFIG_SRIOBOOT_SLAVE
  81 #define CONFIG_ENV_IS_NOWHERE
  82 #endif
  83 #else
  84 #define CONFIG_FLASH_CFI_DRIVER
  85 #define CONFIG_SYS_FLASH_CFI
  86 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  87 #endif
  88
  89 #if defined(CONFIG_SPIFLASH)
  90 #define CONFIG_SYS_EXTRA_ENV_RELOC
  91 #define CONFIG_ENV_IS_IN_SPI_FLASH
  92 #define CONFIG_ENV_SPI_BUS              0
  93 #define CONFIG_ENV_SPI_CS               0
  94 #define CONFIG_ENV_SPI_MAX_HZ           10000000
  95 #define CONFIG_ENV_SPI_MODE             0
  96 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  97 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  98 #define CONFIG_ENV_SECT_SIZE            0x10000
  99 #elif defined(CONFIG_SDCARD)
 100 #define CONFIG_SYS_EXTRA_ENV_RELOC
 101 #define CONFIG_ENV_IS_IN_MMC
 102 #define CONFIG_FSL_FIXED_MMC_LOCATION
 103 #define CONFIG_SYS_MMC_ENV_DEV          0
 104 #define CONFIG_ENV_SIZE                 0x2000
 105 #define CONFIG_ENV_OFFSET               (512 * 1097)
 106 #elif defined(CONFIG_NAND)
 107 #define CONFIG_SYS_EXTRA_ENV_RELOC
 108 #define CONFIG_ENV_IS_IN_NAND
 109 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
 110 #define CONFIG_ENV_OFFSET               (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 111 #elif defined(CONFIG_SRIOBOOT_SLAVE)
 112 #define CONFIG_ENV_IS_IN_REMOTE
 113 #define CONFIG_ENV_ADDR         0xffe20000
 114 #define CONFIG_ENV_SIZE         0x2000
 115 #elif defined(CONFIG_ENV_IS_NOWHERE)
 116 #define CONFIG_ENV_SIZE         0x2000
 117 #else
 118 #define CONFIG_ENV_IS_IN_FLASH
 119 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 120 #define CONFIG_ENV_SIZE         0x2000
 121 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 122 #endif
 123
 124 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 125
 126 /*
 127  * These can be toggled for performance analysis, otherwise use default.
 128  */
 129 #define CONFIG_SYS_CACHE_STASHING
 130 #define CONFIG_BACKSIDE_L2_CACHE
 131 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 132 #define CONFIG_BTB                      /* toggle branch predition */
 133 #define CONFIG_DDR_ECC
 134 #ifdef CONFIG_DDR_ECC
 135 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 136 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 137 #endif
 138
 139 #define CONFIG_ENABLE_36BIT_PHYS
 140
 141 #ifdef CONFIG_PHYS_64BIT
 142 #define CONFIG_ADDR_MAP
 143 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 144 #endif
 145
 146 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 147 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 148 #define CONFIG_SYS_MEMTEST_END          0x00400000
 149 #define CONFIG_SYS_ALT_MEMTEST
 150 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 151
 152 /*
 153  *  Config the L3 Cache as L3 SRAM
 154  */
 155 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 156 #ifdef CONFIG_PHYS_64BIT
 157 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
 158 #else
 159 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 160 #endif
 161 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 162 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 163
 164 #ifdef CONFIG_PHYS_64BIT
 165 #define CONFIG_SYS_DCSRBAR              0xf0000000
 166 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 167 #endif
 168
 169 /* EEPROM */
 170 #define CONFIG_ID_EEPROM
 171 #define CONFIG_SYS_I2C_EEPROM_NXID
 172 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 173 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 174 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 175
 176 /*
 177  * DDR Setup
 178  */
 179 #define CONFIG_VERY_BIG_RAM
 180 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 181 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 182
 183 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 184 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 185
 186 #define CONFIG_DDR_SPD
 187 #define CONFIG_FSL_DDR3
 188
 189 #ifdef CONFIG_P3060QDS
 190 #define CONFIG_SYS_SPD_BUS_NUM  0
 191 #else
 192 #define CONFIG_SYS_SPD_BUS_NUM  1
 193 #endif
 194 #define SPD_EEPROM_ADDRESS1     0x51
 195 #define SPD_EEPROM_ADDRESS2     0x52
 196 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 197 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 198
 199 /*
 200  * Local Bus Definitions
 201  */
 202
 203 /* Set the local bus clock 1/8 of platform clock */
 204 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 205
 206 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* Start of PromJet */
 207 #ifdef CONFIG_PHYS_64BIT
 208 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 209 #else
 210 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 211 #endif
 212
 213 #define CONFIG_SYS_FLASH_BR_PRELIM \
 214                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
 215                  | BR_PS_16 | BR_V)
 216 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 217                                         | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 218
 219 #define CONFIG_SYS_BR1_PRELIM \
 220         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 221 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 222
 223 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 224 #ifdef CONFIG_PHYS_64BIT
 225 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 226 #else
 227 #define PIXIS_BASE_PHYS         PIXIS_BASE
 228 #endif
 229
 230 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 231 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 232
 233 #define PIXIS_LBMAP_SWITCH      7
 234 #define PIXIS_LBMAP_MASK        0xf0
 235 #define PIXIS_LBMAP_SHIFT       4
 236 #define PIXIS_LBMAP_ALTBANK     0x40
 237
 238 #define CONFIG_SYS_FLASH_QUIET_TEST
 239 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 240
 241 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 242 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 243 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 244 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 245
 246 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 247
 248 #if defined(CONFIG_RAMBOOT_PBL)
 249 #define CONFIG_SYS_RAMBOOT
 250 #endif
 251
 252 /* Nand Flash */
 253 #ifdef CONFIG_NAND_FSL_ELBC
 254 #define CONFIG_SYS_NAND_BASE            0xffa00000
 255 #ifdef CONFIG_PHYS_64BIT
 256 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 257 #else
 258 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 259 #endif
 260
 261 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 262 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 263 #define CONFIG_MTD_NAND_VERIFY_WRITE
 264 #define CONFIG_CMD_NAND
 265 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 266
 267 /* NAND flash config */
 268 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 269                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 270                                | BR_PS_8               /* Port Size = 8 bit */ \
 271                                | BR_MS_FCM             /* MSEL = FCM */ \
 272                                | BR_V)                 /* valid */
 273 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 274                                | OR_FCM_PGS            /* Large Page*/ \
 275                                | OR_FCM_CSCT \
 276                                | OR_FCM_CST \
 277                                | OR_FCM_CHT \
 278                                | OR_FCM_SCY_1 \
 279                                | OR_FCM_TRLX \
 280                                | OR_FCM_EHTR)
 281
 282 #ifdef CONFIG_NAND
 283 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 284 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 285 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 286 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 287 #else
 288 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 289 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 290 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 291 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 292 #endif
 293 #else
 294 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 295 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 296 #endif /* CONFIG_NAND_FSL_ELBC */
 297
 298 #define CONFIG_SYS_FLASH_EMPTY_INFO
 299 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 300 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 301
 302 #define CONFIG_BOARD_EARLY_INIT_F
 303 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 304 #define CONFIG_MISC_INIT_R
 305
 306 #define CONFIG_HWCONFIG
 307
 308 /* define to use L1 as initial stack */
 309 #define CONFIG_L1_INIT_RAM
 310 #define CONFIG_SYS_INIT_RAM_LOCK
 311 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 312 #ifdef CONFIG_PHYS_64BIT
 313 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 314 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 315 /* The assembler doesn't like typecast */
 316 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 317         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 318           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 319 #else
 320 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 321 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 322 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 323 #endif
 324 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 325
 326 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 327 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 328
 329 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 330 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 331
 332 /* Serial Port - controlled on board with jumper J8
 333  * open - index 2
 334  * shorted - index 1
 335  */
 336 #define CONFIG_CONS_INDEX       1
 337 #define CONFIG_SYS_NS16550
 338 #define CONFIG_SYS_NS16550_SERIAL
 339 #define CONFIG_SYS_NS16550_REG_SIZE     1
 340 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 341
 342 #define CONFIG_SYS_BAUDRATE_TABLE       \
 343         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 344
 345 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 346 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 347 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 348 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 349
 350 /* Use the HUSH parser */
 351 #define CONFIG_SYS_HUSH_PARSER
 352
 353 /* pass open firmware flat tree */
 354 #define CONFIG_OF_LIBFDT
 355 #define CONFIG_OF_BOARD_SETUP
 356 #define CONFIG_OF_STDOUT_VIA_ALIAS
 357
 358 /* new uImage format support */
 359 #define CONFIG_FIT
 360 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 361
 362 /* I2C */
 363 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 364 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 365 #define CONFIG_I2C_MULTI_BUS
 366 #define CONFIG_I2C_CMD_TREE
 367 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 368 #define CONFIG_SYS_I2C_SLAVE            0x7F
 369 #define CONFIG_SYS_I2C_OFFSET           0x118000
 370 #define CONFIG_SYS_I2C2_OFFSET          0x118100
 371
 372 /*
 373  * RapidIO
 374  */
 375 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 376 #ifdef CONFIG_PHYS_64BIT
 377 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 378 #else
 379 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 380 #endif
 381 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 382
 383 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 384 #ifdef CONFIG_PHYS_64BIT
 385 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 386 #else
 387 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 388 #endif
 389 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 390
 391 /*
 392  * SRIOBOOT - MASTER
 393  */
 394 #ifdef CONFIG_SRIOBOOT_MASTER
 395 /* master port for srioboot*/
 396 #define CONFIG_SRIOBOOT_MASTER_PORT 0
 397 /* #define CONFIG_SRIOBOOT_MASTER_PORT 1 */
 398 /*
 399  * for slave u-boot IMAGE instored in master memory space,
 400  * PHYS must be aligned based on the SIZE
 401  */
 402 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 0xfef080000ull
 403 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 0xfff80000ull
 404 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000        /* 512K */
 405 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull
 406 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull
 407 /*
 408  * for slave UCODE instored in master memory space,
 409  * PHYS must be aligned based on the SIZE
 410  */
 411 #define CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 0xfef020000ull
 412 #define CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 0x3ffe00000ull
 413 #define CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE 0x10000        /* 64K */
 414 /*
 415  * for slave ENV instored in master memory space,
 416  * PHYS must be aligned based on the SIZE
 417  */
 418 #define CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 0xfef060000ull
 419 #define CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 0x3ffe20000ull
 420 #define CONFIG_SRIOBOOT_SLAVE_ENV_SIZE 0x20000  /* 128K */
 421 /* slave core release by master*/
 422 #define CONFIG_SRIOBOOT_SLAVE_HOLDOFF
 423 #define CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET 0xe00e4
 424 #define CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK 0x00000001 /* release core 0 */
 425 #endif
 426
 427 /*
 428  * SRIOBOOT - SLAVE
 429  */
 430 #ifdef CONFIG_SRIOBOOT_SLAVE
 431 /* slave port for srioboot */
 432 #define CONFIG_SRIOBOOT_SLAVE_PORT0
 433 /* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */
 434 #define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE00000
 435 #define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \
 436                 (0x300000000ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR)
 437 #endif
 438
 439 /*
 440  * eSPI - Enhanced SPI
 441  */
 442 #define CONFIG_FSL_ESPI
 443 #define CONFIG_SPI_FLASH
 444 #define CONFIG_SPI_FLASH_SPANSION
 445 #define CONFIG_CMD_SF
 446 #define CONFIG_SF_DEFAULT_SPEED         10000000
 447 #define CONFIG_SF_DEFAULT_MODE          0
 448
 449 /*
 450  * General PCI
 451  * Memory space is mapped 1-1, but I/O space must start from 0.
 452  */
 453
 454 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 455 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 456 #ifdef CONFIG_PHYS_64BIT
 457 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 458 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 459 #else
 460 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 461 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 462 #endif
 463 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 464 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 465 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 466 #ifdef CONFIG_PHYS_64BIT
 467 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 468 #else
 469 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 470 #endif
 471 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 472
 473 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 474 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 475 #ifdef CONFIG_PHYS_64BIT
 476 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 477 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 478 #else
 479 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 480 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 481 #endif
 482 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 483 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 484 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 485 #ifdef CONFIG_PHYS_64BIT
 486 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 487 #else
 488 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 489 #endif
 490 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 491
 492 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 493 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 494 #ifdef CONFIG_PHYS_64BIT
 495 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 496 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 497 #else
 498 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 499 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 500 #endif
 501 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 502 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 503 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 504 #ifdef CONFIG_PHYS_64BIT
 505 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 506 #else
 507 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 508 #endif
 509 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 510
 511 /* controller 4, Base address 203000 */
 512 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 513 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 514 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 515 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 516 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 517 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 518
 519 /* Qman/Bman */
 520 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 521 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 522 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 523 #ifdef CONFIG_PHYS_64BIT
 524 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 525 #else
 526 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 527 #endif
 528 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 529 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 530 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 531 #ifdef CONFIG_PHYS_64BIT
 532 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 533 #else
 534 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 535 #endif
 536 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 537
 538 #define CONFIG_SYS_DPAA_FMAN
 539 #define CONFIG_SYS_DPAA_PME
 540 /* Default address of microcode for the Linux Fman driver */
 541 #if defined(CONFIG_SPIFLASH)
 542 /*
 543  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 544  * env, so we got 0x110000.
 545  */
 546 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 547 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0x110000
 548 #elif defined(CONFIG_SDCARD)
 549 /*
 550  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 551  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
 552  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
 553  */
 554 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 555 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (512 * 1130)
 556 #elif defined(CONFIG_NAND)
 557 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 558 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
 559 #elif defined(CONFIG_SRIOBOOT_SLAVE)
 560 /*
 561  * Slave has no ucode locally, it can fetch this from remote. When implementing
 562  * in two corenet boards, slave's ucode could be stored in master's memory
 563  * space, the address can be mapped from slave TLB->slave LAW->
 564  * slave SRIO outbound window->master inbound window->master LAW->
 565  * the ucode address in master's NOR flash.
 566  */
 567 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 568 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0xFFE00000
 569 #else
 570 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 571 #define CONFIG_SYS_QE_FMAN_FW_ADDR              0xEF000000
 572 #endif
 573 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 574 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 575
 576 #ifdef CONFIG_SYS_DPAA_FMAN
 577 #define CONFIG_FMAN_ENET
 578 #define CONFIG_PHYLIB_10G
 579 #define CONFIG_PHY_VITESSE
 580 #define CONFIG_PHY_TERANETICS
 581 #endif
 582
 583 #ifdef CONFIG_PCI
 584 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 585 #define CONFIG_E1000
 586
 587 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 588 #define CONFIG_DOS_PARTITION
 589 #endif  /* CONFIG_PCI */
 590
 591 /* SATA */
 592 #ifdef CONFIG_FSL_SATA_V2
 593 #define CONFIG_LIBATA
 594 #define CONFIG_FSL_SATA
 595
 596 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 597 #define CONFIG_SATA1
 598 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 599 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 600 #define CONFIG_SATA2
 601 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 602 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 603
 604 #define CONFIG_LBA48
 605 #define CONFIG_CMD_SATA
 606 #define CONFIG_DOS_PARTITION
 607 #define CONFIG_CMD_EXT2
 608 #endif
 609
 610 #ifdef CONFIG_FMAN_ENET
 611 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1c
 612 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x1d
 613 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x1e
 614 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1f
 615 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  4
 616
 617 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR  0x1c
 618 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR  0x1d
 619 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR  0x1e
 620 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR  0x1f
 621 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR  0
 622
 623 #define CONFIG_SYS_TBIPA_VALUE  8
 624 #define CONFIG_MII              /* MII PHY management */
 625 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 626 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 627 #endif
 628
 629 /*
 630  * Environment
 631  */
 632 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 633 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 634
 635 /*
 636  * Command line configuration.
 637  */
 638 #include <config_cmd_default.h>
 639
 640 #define CONFIG_CMD_DHCP
 641 #define CONFIG_CMD_ELF
 642 #define CONFIG_CMD_ERRATA
 643 #define CONFIG_CMD_GREPENV
 644 #define CONFIG_CMD_IRQ
 645 #define CONFIG_CMD_I2C
 646 #define CONFIG_CMD_MII
 647 #define CONFIG_CMD_PING
 648 #define CONFIG_CMD_SETEXPR
 649 #define CONFIG_CMD_REGINFO
 650
 651 #ifdef CONFIG_PCI
 652 #define CONFIG_CMD_PCI
 653 #define CONFIG_CMD_NET
 654 #endif
 655
 656 /*
 657 * USB
 658 */
 659 #define CONFIG_HAS_FSL_DR_USB
 660 #define CONFIG_HAS_FSL_MPH_USB
 661
 662 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 663 #define CONFIG_CMD_USB
 664 #define CONFIG_USB_STORAGE
 665 #define CONFIG_USB_EHCI
 666 #define CONFIG_USB_EHCI_FSL
 667 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 668 #define CONFIG_CMD_EXT2
 669 #endif
 670
 671 #ifdef CONFIG_MMC
 672 #define CONFIG_FSL_ESDHC
 673 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 674 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 675 #define CONFIG_CMD_MMC
 676 #define CONFIG_GENERIC_MMC
 677 #define CONFIG_CMD_EXT2
 678 #define CONFIG_CMD_FAT
 679 #define CONFIG_DOS_PARTITION
 680 #endif
 681
 682 /*
 683  * Miscellaneous configurable options
 684  */
 685 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 686 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 687 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 688 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 689 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 690 #ifdef CONFIG_CMD_KGDB
 691 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 692 #else
 693 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 694 #endif
 695 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 696 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 697 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 698 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 699
 700 /*
 701  * For booting Linux, the board info and command line data
 702  * have to be in the first 64 MB of memory, since this is
 703  * the maximum mapped by the Linux kernel during initialization.
 704  */
 705 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 706 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 707
 708 #ifdef CONFIG_CMD_KGDB
 709 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 710 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 711 #endif
 712
 713 /*
 714  * Environment Configuration
 715  */
 716 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 717 #define CONFIG_BOOTFILE         "uImage"
 718 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 719
 720 /* default location for tftp and bootm */
 721 #define CONFIG_LOADADDR         1000000
 722
 723 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 724
 725 #define CONFIG_BAUDRATE 115200
 726
 727 #if defined(CONFIG_P4080DS) || defined(CONFIG_P3060QDS)
 728 #define __USB_PHY_TYPE  ulpi
 729 #else
 730 #define __USB_PHY_TYPE  utmi
 731 #endif
 732
 733 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 734         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 735         "bank_intlv=cs0_cs1;"                                   \
 736         "usb1:dr_mode=host,phy_type=" MK_STR(__USB_PHY_TYPE) "\0"\
 737         "netdev=eth0\0"                                         \
 738         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                  \
 739         "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0"                  \
 740         "tftpflash=tftpboot $loadaddr $uboot && "               \
 741         "protect off $ubootaddr +$filesize && "                 \
 742         "erase $ubootaddr +$filesize && "                       \
 743         "cp.b $loadaddr $ubootaddr $filesize && "               \
 744         "protect on $ubootaddr +$filesize && "                  \
 745         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 746         "consoledev=ttyS0\0"                                    \
 747         "ramdiskaddr=2000000\0"                                 \
 748         "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
 749         "fdtaddr=c00000\0"                                      \
 750         "fdtfile=p4080ds/p4080ds.dtb\0"                         \
 751         "bdev=sda3\0"                                           \
 752         "c=ffe\0"
 753
 754 #define CONFIG_HDBOOT                                   \
 755         "setenv bootargs root=/dev/$bdev rw "           \
 756         "console=$consoledev,$baudrate $othbootargs;"   \
 757         "tftp $loadaddr $bootfile;"                     \
 758         "tftp $fdtaddr $fdtfile;"                       \
 759         "bootm $loadaddr - $fdtaddr"
 760
 761 #define CONFIG_NFSBOOTCOMMAND                   \
 762         "setenv bootargs root=/dev/nfs rw "     \
 763         "nfsroot=$serverip:$rootpath "          \
 764         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 765         "console=$consoledev,$baudrate $othbootargs;"   \
 766         "tftp $loadaddr $bootfile;"             \
 767         "tftp $fdtaddr $fdtfile;"               \
 768         "bootm $loadaddr - $fdtaddr"
 769
 770 #define CONFIG_RAMBOOTCOMMAND                           \
 771         "setenv bootargs root=/dev/ram rw "             \
 772         "console=$consoledev,$baudrate $othbootargs;"   \
 773         "tftp $ramdiskaddr $ramdiskfile;"               \
 774         "tftp $loadaddr $bootfile;"                     \
 775         "tftp $fdtaddr $fdtfile;"                       \
 776         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 777
 778 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 779
 780 #ifdef CONFIG_SECURE_BOOT
 781 #include <asm/fsl_secure_boot.h>
 782 #endif
 783
 784 #endif  /* __CONFIG_H */