include/configs/csb226.h

   1 /*
   2  * (C) Copyright 2000, 2001, 2002
   3  * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
   4  *
   5  * Configuration for the Cogent CSB226 board. For details see
   6  * http://www.cogcomp.com/csb_csb226.htm
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * include/configs/csb226.h - configuration options, board specific
  29  */
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 #define DEBUG 1
  35
  36 /*
  37  * High Level Configuration Options
  38  * (easy to change)
  39  */
  40 #define CONFIG_PXA250           1       /* This is an PXA250 CPU            */
  41 #define CONFIG_CSB226           1       /* on a CSB226 board                */
  42
  43 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff      */
  44                                         /* for timer/console/ethernet       */
  45 /*
  46  * Hardware drivers
  47  */
  48
  49 /*
  50  * select serial console configuration
  51  */
  52 #define CONFIG_FFUART           1       /* we use FFUART on CSB226          */
  53
  54 /* allow to overwrite serial and ethaddr */
  55 #define CONFIG_ENV_OVERWRITE
  56
  57 #define CONFIG_BAUDRATE         19200
  58 #undef  CONFIG_MISC_INIT_R              /* not used yet                     */
  59
  60 #define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_DHCP|CFG_CMD_CACHE)
  61
  62 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  63 #include <cmd_confdefs.h>
  64
  65 #define CONFIG_BOOTDELAY        3
  66 #define CONFIG_BOOTARGS         "console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0"
  67 #define CONFIG_ETHADDR          FF:FF:FF:FF:FF:FF
  68 #define CONFIG_NETMASK          255.255.255.0
  69 #define CONFIG_IPADDR           192.168.1.56
  70 #define CONFIG_SERVERIP         192.168.1.5
  71 #define CONFIG_BOOTCOMMAND      "bootm 0x40000"
  72 #define CONFIG_SHOW_BOOT_PROGRESS
  73
  74 #define CONFIG_CMDLINE_TAG      1
  75
  76 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  77 #define CONFIG_KGDB_BAUDRATE    19200           /* speed to run kgdb serial port */
  78 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
  79 #endif
  80
  81 /*
  82  * Miscellaneous configurable options
  83  */
  84
  85 /*
  86  * Size of malloc() pool; this lives below the uppermost 128 KiB which are
  87  * used for the RAM copy of the uboot code
  88  *
  89  */
  90 #define CFG_MALLOC_LEN          (128*1024)
  91 #define CFG_GBL_DATA_SIZE       128             /* size in bytes reserved for initial data */
  92
  93 #define CFG_LONGHELP                            /* undef to save memory         */
  94 #define CFG_PROMPT              "uboot> "       /* Monitor Command Prompt       */
  95 #define CFG_CBSIZE              128             /* Console I/O Buffer Size      */
  96 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  97 #define CFG_MAXARGS             16              /* max number of command args   */
  98 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
  99
 100 #define CFG_MEMTEST_START       0xa0400000      /* memtest works on     */
 101 #define CFG_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
 102
 103 #undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 104
 105 #define CFG_LOAD_ADDR           0xa3000000      /* default load address */
 106                                                 /* RS: where is this documented? */
 107                                                 /* RS: is this where U-Boot is  */
 108                                                 /* RS: relocated to in RAM?      */
 109
 110 #define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
 111                                                 /* RS: the oscillator is actually 3680130?? */
 112 #define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
 113                                                 /* 0101000001 */
 114                                                 /*      ^^^^^ Memory Speed 99.53 MHz         */
 115                                                 /*    ^^      Run Mode Speed = 2x Mem Speed  */
 116                                                 /* ^^         Turbo Mode Sp. = 1x Run M. Sp. */
 117
 118 #define CFG_MONITOR_LEN         0x20000         /* 128 KiB */
 119
 120                                                 /* valid baudrates */
 121 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 122
 123 /*
 124  * Network chip
 125  */
 126 #define CONFIG_DRIVER_CS8900    1
 127 #define CS8900_BUS32            1
 128 #define CS8900_BASE             0x08000000
 129
 130 /*
 131  * Stack sizes
 132  *
 133  * The stack sizes are set up in start.S using the settings below
 134  */
 135 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 136 #ifdef  CONFIG_USE_IRQ
 137 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 138 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 139 #endif
 140
 141 /*
 142  * Physical Memory Map
 143  */
 144 #define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of DRAM   */
 145 #define PHYS_SDRAM_1            0xa0000000      /* SDRAM Bank #1            */
 146 #define PHYS_SDRAM_1_SIZE       0x02000000      /* 32 MB                    */
 147
 148 #define PHYS_FLASH_1            0x00000000      /* Flash Bank #1            */
 149 #define PHYS_FLASH_SIZE         0x02000000      /* 32 MB                    */
 150
 151 #define CFG_DRAM_BASE           0xa0000000      /* RAM starts here          */
 152 #define CFG_DRAM_SIZE           0x02000000
 153
 154 #define CFG_FLASH_BASE          PHYS_FLASH_1
 155
 156 # if 0
 157 /* FIXME: switch to _documented_ registers */
 158 /*
 159  * GPIO settings
 160  *
 161  * GP15 == nCS1      is 1
 162  * GP24 == SFRM      is 1
 163  * GP25 == TXD       is 1
 164  * GP33 == nCS5      is 1
 165  * GP39 == FFTXD     is 1
 166  * GP41 == RTS       is 1
 167  * GP47 == TXD       is 1
 168  * GP49 == nPWE      is 1
 169  * GP62 == LED_B     is 1
 170  * GP63 == TDM_OE    is 1
 171  * GP78 == nCS2      is 1
 172  * GP79 == nCS3      is 1
 173  * GP80 == nCS4      is 1
 174  */
 175 #define CFG_GPSR0_VAL       0x03008000
 176 #define CFG_GPSR1_VAL       0xC0028282
 177 #define CFG_GPSR2_VAL       0x0001C000
 178
 179 /* GP02 == DON_RST   is 0
 180  * GP23 == SCLK      is 0
 181  * GP45 == USB_ACT   is 0
 182  * GP60 == PLLEN     is 0
 183  * GP61 == LED_A     is 0
 184  * GP73 == SWUPD_LED is 0
 185  */
 186 #define CFG_GPCR0_VAL       0x00800004
 187 #define CFG_GPCR1_VAL       0x30002000
 188 #define CFG_GPCR2_VAL       0x00000100
 189
 190 /* GP00 == DON_READY is input
 191  * GP01 == DON_OK    is input
 192  * GP02 == DON_RST   is output
 193  * GP03 == RESET_IND is input
 194  * GP07 == RES11     is input
 195  * GP09 == RES12     is input
 196  * GP11 == SWUPDATE  is input
 197  * GP14 == nPOWEROK  is input
 198  * GP15 == nCS1      is output
 199  * GP17 == RES22     is input
 200  * GP18 == RDY       is input
 201  * GP23 == SCLK      is output
 202  * GP24 == SFRM      is output
 203  * GP25 == TXD       is output
 204  * GP26 == RXD       is input
 205  * GP32 == RES21     is input
 206  * GP33 == nCS5      is output
 207  * GP34 == FFRXD     is input
 208  * GP35 == CTS       is input
 209  * GP39 == FFTXD     is output
 210  * GP41 == RTS       is output
 211  * GP42 == USB_OK    is input
 212  * GP45 == USB_ACT   is output
 213  * GP46 == RXD       is input
 214  * GP47 == TXD       is output
 215  * GP49 == nPWE      is output
 216  * GP58 == nCPUBUSINT is input
 217  * GP59 == LANINT    is input
 218  * GP60 == PLLEN     is output
 219  * GP61 == LED_A     is output
 220  * GP62 == LED_B     is output
 221  * GP63 == TDM_OE    is output
 222  * GP64 == nDSPINT   is input
 223  * GP65 == STRAP0    is input
 224  * GP67 == STRAP1    is input
 225  * GP69 == STRAP2    is input
 226  * GP70 == STRAP3    is input
 227  * GP71 == STRAP4    is input
 228  * GP73 == SWUPD_LED is output
 229  * GP78 == nCS2      is output
 230  * GP79 == nCS3      is output
 231  * GP80 == nCS4      is output
 232  */
 233 #define CFG_GPDR0_VAL       0x03808004
 234 #define CFG_GPDR1_VAL       0xF002A282
 235 #define CFG_GPDR2_VAL       0x0001C200
 236
 237 /* GP15 == nCS1  is AF10
 238  * GP18 == RDY   is AF01
 239  * GP23 == SCLK  is AF10
 240  * GP24 == SFRM  is AF10
 241  * GP25 == TXD   is AF10
 242  * GP26 == RXD   is AF01
 243  * GP33 == nCS5  is AF10
 244  * GP34 == FFRXD is AF01
 245  * GP35 == CTS   is AF01
 246  * GP39 == FFTXD is AF10
 247  * GP41 == RTS   is AF10
 248  * GP46 == RXD   is AF10
 249  * GP47 == TXD   is AF01
 250  * GP49 == nPWE  is AF10
 251  * GP78 == nCS2  is AF10
 252  * GP79 == nCS3  is AF10
 253  * GP80 == nCS4  is AF10
 254  */
 255 #define CFG_GAFR0_L_VAL     0x80000000
 256 #define CFG_GAFR0_U_VAL     0x001A8010
 257 #define CFG_GAFR1_L_VAL     0x60088058
 258 #define CFG_GAFR1_U_VAL     0x00000008
 259 #define CFG_GAFR2_L_VAL     0xA0000000
 260 #define CFG_GAFR2_U_VAL     0x00000002
 261
 262
 263 /* FIXME: set GPIO_RER/FER */
 264
 265 /* RDH = 1
 266  * PH  = 1
 267  * VFS = 1
 268  * BFS = 1
 269  * SSS = 1
 270  */
 271 #define CFG_PSSR_VAL            0x37
 272
 273 /*
 274  * Memory settings
 275  *
 276  * This is the configuration for nCS0/1 -> flash banks
 277  * configuration for nCS1:
 278  * [31]    0    - Slower Device
 279  * [30:28] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
 280  * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
 281  * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
 282  * [19]    1    - 16 Bit bus width
 283  * [18:16] 000  - nonburst RAM or FLASH
 284  * configuration for nCS0:
 285  * [15]    0    - Slower Device
 286  * [14:12] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
 287  * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
 288  * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
 289  * [03]    1    - 16 Bit bus width
 290  * [02:00] 000  - nonburst RAM or FLASH
 291  */
 292 #define CFG_MSC0_VAL            0x25b825b8 /* flash banks                   */
 293
 294 /* This is the configuration for nCS2/3 -> TDM-Switch, DSP
 295  * configuration for nCS3: DSP
 296  * [31]    0    - Slower Device
 297  * [30:28] 001  - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
 298  * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 299  * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
 300  * [19]    1    - 16 Bit bus width
 301  * [18:16] 100  - variable latency I/O
 302  * configuration for nCS2: TDM-Switch
 303  * [15]    0    - Slower Device
 304  * [14:12] 101  - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
 305  * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
 306  * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
 307  * [03]    1    - 16 Bit bus width
 308  * [02:00] 100  - variable latency I/O
 309  */
 310 #define CFG_MSC1_VAL            0x123C593C /* TDM switch, DSP               */
 311
 312 /* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
 313  *
 314  * configuration for nCS5: LAN Controller
 315  * [31]    0    - Slower Device
 316  * [30:28] 001  - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
 317  * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 318  * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
 319  * [19]    1    - 16 Bit bus width
 320  * [18:16] 100  - variable latency I/O
 321  * configuration for nCS4: ExtBus
 322  * [15]    0    - Slower Device
 323  * [14:12] 110  - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
 324  * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
 325  * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
 326  * [03]    1    - 16 Bit bus width
 327  * [02:00] 100  - variable latency I/O
 328  */
 329 #define CFG_MSC2_VAL            0x123C6CDC /* extra bus, LAN controller     */
 330
 331 /* MDCNFG: SDRAM Configuration Register
 332  *
 333  * [31:29]   000 - reserved
 334  * [28]      0   - no SA1111 compatiblity mode
 335  * [27]      0   - latch return data with return clock
 336  * [26]      0   - alternate addressing for pair 2/3
 337  * [25:24]   00  - timings
 338  * [23]      0   - internal banks in lower partition 2/3 (not used)
 339  * [22:21]   00  - row address bits for partition 2/3 (not used)
 340  * [20:19]   00  - column address bits for partition 2/3 (not used)
 341  * [18]      0   - SDRAM partition 2/3 width is 32 bit
 342  * [17]      0   - SDRAM partition 3 disabled
 343  * [16]      0   - SDRAM partition 2 disabled
 344  * [15:13]   000 - reserved
 345  * [12]      1   - SA1111 compatiblity mode
 346  * [11]      1   - latch return data with return clock
 347  * [10]      0   - no alternate addressing for pair 0/1
 348  * [09:08]   01  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
 349  * [7]       1   - 4 internal banks in lower partition pair
 350  * [06:05]   10  - 13 row address bits for partition 0/1
 351  * [04:03]   01  - 9 column address bits for partition 0/1
 352  * [02]      0   - SDRAM partition 0/1 width is 32 bit
 353  * [01]      0   - disable SDRAM partition 1
 354  * [00]      1   - enable  SDRAM partition 0
 355  */
 356 /* use the configuration above but disable partition 0 */
 357 #define CFG_MDCNFG_VAL          0x000019c8
 358
 359 /* MDREFR: SDRAM Refresh Control Register
 360  *
 361  * [32:26] 0     - reserved
 362  * [25]    0     - K2FREE: not free running
 363  * [24]    0     - K1FREE: not free running
 364  * [23]    1     - K0FREE: not free running
 365  * [22]    0     - SLFRSH: self refresh disabled
 366  * [21]    0     - reserved
 367  * [20]    0     - APD: no auto power down
 368  * [19]    0     - K2DB2: SDCLK2 is MemClk
 369  * [18]    0     - K2RUN: disable SDCLK2
 370  * [17]    0     - K1DB2: SDCLK1 is MemClk
 371  * [16]    1     - K1RUN: enable SDCLK1
 372  * [15]    1     - E1PIN: SDRAM clock enable
 373  * [14]    1     - K0DB2: SDCLK0 is MemClk
 374  * [13]    0     - K0RUN: disable SDCLK0
 375  * [12]    1     - E0PIN: disable SDCKE0
 376  * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
 377  */
 378 #define CFG_MDREFR_VAL          0x0081D018
 379
 380 /* MDMRS: Mode Register Set Configuration Register
 381  *
 382  * [31]      0       - reserved
 383  * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
 384  * [22:20]   000     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
 385  * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
 386  * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
 387  * [15]      0       - reserved
 388  * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
 389  * [06:04]   010     - MDCL0:  SDRAM0/1 Cas Latency.
 390  * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
 391  * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
 392  */
 393 #define CFG_MDMRS_VAL           0x00020022
 394
 395 /*
 396  * PCMCIA and CF Interfaces
 397  */
 398 #define CFG_MECR_VAL            0x00000000
 399 #define CFG_MCMEM0_VAL          0x00000000
 400 #define CFG_MCMEM1_VAL          0x00000000
 401 #define CFG_MCATT0_VAL          0x00000000
 402 #define CFG_MCATT1_VAL          0x00000000
 403 #define CFG_MCIO0_VAL           0x00000000
 404 #define CFG_MCIO1_VAL           0x00000000
 405 #endif
 406
 407 /*
 408  * GPIO settings
 409  */
 410 #define CFG_GPSR0_VAL           0xFFFFFFFF
 411 #define CFG_GPSR1_VAL           0xFFFFFFFF
 412 #define CFG_GPSR2_VAL           0xFFFFFFFF
 413 #define CFG_GPCR0_VAL           0x08022080
 414 #define CFG_GPCR1_VAL           0x00000000
 415 #define CFG_GPCR2_VAL           0x00000000
 416 #define CFG_GPDR0_VAL           0xCD82A878
 417 #define CFG_GPDR1_VAL           0xFCFFAB80
 418 #define CFG_GPDR2_VAL           0x0001FFFF
 419 #define CFG_GAFR0_L_VAL         0x80000000
 420 #define CFG_GAFR0_U_VAL         0xA5254010
 421 #define CFG_GAFR1_L_VAL         0x599A9550
 422 #define CFG_GAFR1_U_VAL         0xAAA5AAAA
 423 #define CFG_GAFR2_L_VAL         0xAAAAAAAA
 424 #define CFG_GAFR2_U_VAL         0x00000002
 425
 426 /* FIXME: set GPIO_RER/FER */
 427
 428 #define CFG_PSSR_VAL        0x20
 429
 430 /*
 431  * Memory settings
 432  */
 433
 434 #define CFG_MSC0_VAL            0x2ef15af0
 435 #define CFG_MSC1_VAL            0x00003ff4
 436 #define CFG_MSC2_VAL            0x7ff07ff0
 437 #define CFG_MDCNFG_VAL          0x09a909a9
 438 #define CFG_MDREFR_VAL          0x038ff030
 439 #define CFG_MDMRS_VAL           0x00220022
 440
 441 /*
 442  * PCMCIA and CF Interfaces
 443  */
 444 #define CFG_MECR_VAL        0x00000000
 445 #define CFG_MCMEM0_VAL      0x00000000
 446 #define CFG_MCMEM1_VAL      0x00000000
 447 #define CFG_MCATT0_VAL      0x00000000
 448 #define CFG_MCATT1_VAL      0x00000000
 449 #define CFG_MCIO0_VAL       0x00000000
 450 #define CFG_MCIO1_VAL       0x00000000
 451
 452 #define CSB226_USER_LED0        0x00000008
 453 #define CSB226_USER_LED1        0x00000010
 454 #define CSB226_USER_LED2        0x00000020
 455
 456
 457 /*
 458  * FLASH and environment organization
 459  */
 460 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks       */
 461 #define CFG_MAX_FLASH_SECT      128     /* max number of sect. on one chip  */
 462
 463 /* timeout values are in ticks */
 464 #define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase       */
 465 #define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write       */
 466
 467 #define CFG_ENV_IS_IN_FLASH     1
 468 #define CFG_ENV_ADDR            (PHYS_FLASH_1 + 0x1C000)
 469                                         /* Addr of Environment Sector       */
 470 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector */
 471
 472 #endif  /* __CONFIG_H */