include/configs/cyrus.h

   1 /*
   2  * Based on corenet_ds.h
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_DISPLAY_BOARDINFO
  11
  12 #define CONFIG_CYRUS
  13
  14 #define CONFIG_PHYS_64BIT
  15
  16 #if !defined(CONFIG_PPC_P5020) && !defined(CONFIG_PPC_P5040)
  17 #error Must call Cyrus CONFIG with a specific CPU enabled.
  18 #endif
  19
  20
  21 #define CONFIG_MMC
  22 #define CONFIG_SDCARD
  23 #define CONFIG_FSL_SATA_V2
  24 #define CONFIG_PCIE3
  25 #define CONFIG_PCIE4
  26 #ifdef CONFIG_PPC_P5020
  27 #define CONFIG_SYS_FSL_RAID_ENGINE
  28 #define CONFIG_SYS_DPAA_RMAN
  29 #endif
  30 #define CONFIG_SYS_DPAA_PME
  31
  32 /*
  33  * Corenet DS style board configuration file
  34  */
  35 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  36 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  37 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
  38 #if defined(CONFIG_PPC_P5020)
  39 #define CONFIG_SYS_CLK_FREQ 133000000
  40 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
  41 #elif defined(CONFIG_PPC_P5040)
  42 #define CONFIG_SYS_CLK_FREQ 100000000
  43 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
  44 #endif
  45
  46
  47 /* High Level Configuration Options */
  48 #define CONFIG_BOOKE
  49 #define CONFIG_E500                     /* BOOKE e500 family */
  50 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  51 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  52 #define CONFIG_MP                       /* support multiple processors */
  53
  54
  55 #define CONFIG_SYS_MMC_MAX_DEVICE     1
  56
  57 #ifndef CONFIG_SYS_TEXT_BASE
  58 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  59 #endif
  60
  61 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  62 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  63 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
  64 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  65 #define CONFIG_PCIE1                    /* PCIE controler 1 */
  66 #define CONFIG_PCIE2                    /* PCIE controler 2 */
  67 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  68 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  69
  70 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  71
  72 #define CONFIG_ENV_OVERWRITE
  73
  74 #define CONFIG_SYS_NO_FLASH
  75
  76 #if defined(CONFIG_SDCARD)
  77 #define CONFIG_SYS_EXTRA_ENV_RELOC
  78 #define CONFIG_ENV_IS_IN_MMC
  79 #define CONFIG_FSL_FIXED_MMC_LOCATION
  80 #define CONFIG_SYS_MMC_ENV_DEV          0
  81 #define CONFIG_ENV_SIZE                 0x2000
  82 #define CONFIG_ENV_OFFSET               (512 * 1658)
  83 #endif
  84
  85 /*
  86  * These can be toggled for performance analysis, otherwise use default.
  87  */
  88 #define CONFIG_SYS_CACHE_STASHING
  89 #define CONFIG_BACKSIDE_L2_CACHE
  90 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  91 #define CONFIG_BTB                      /* toggle branch predition */
  92 #define CONFIG_DDR_ECC
  93 #ifdef CONFIG_DDR_ECC
  94 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  95 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  96 #endif
  97
  98 #define CONFIG_ENABLE_36BIT_PHYS
  99
 100 #ifdef CONFIG_PHYS_64BIT
 101 #define CONFIG_ADDR_MAP
 102 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 103 #endif
 104
 105 /* test POST memory test */
 106 #undef CONFIG_POST
 107 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 108 #define CONFIG_SYS_MEMTEST_END          0x00400000
 109 #define CONFIG_SYS_ALT_MEMTEST
 110 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 111
 112 /*
 113  *  Config the L3 Cache as L3 SRAM
 114  */
 115 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 116 #ifdef CONFIG_PHYS_64BIT
 117 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
 118 #else
 119 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 120 #endif
 121 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 122 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 123
 124 #ifdef CONFIG_PHYS_64BIT
 125 #define CONFIG_SYS_DCSRBAR              0xf0000000
 126 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 127 #endif
 128
 129 /*
 130  * DDR Setup
 131  */
 132 #define CONFIG_VERY_BIG_RAM
 133 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 134 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 135
 136 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 137 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 138
 139 #define CONFIG_DDR_SPD
 140 #define CONFIG_SYS_FSL_DDR3
 141
 142 #define CONFIG_SYS_SPD_BUS_NUM  1
 143 #define SPD_EEPROM_ADDRESS1     0x51
 144 #define SPD_EEPROM_ADDRESS2     0x52
 145 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 146
 147 /*
 148  * Local Bus Definitions
 149  */
 150
 151 #define CONFIG_SYS_LBC0_BASE            0xe0000000 /* Start of LBC Registers */
 152 #ifdef CONFIG_PHYS_64BIT
 153 #define CONFIG_SYS_LBC0_BASE_PHYS       0xfe0000000ull
 154 #else
 155 #define CONFIG_SYS_LBC0_BASE_PHYS       CONFIG_SYS_LBC0_BASE
 156 #endif
 157
 158 #define CONFIG_SYS_LBC1_BASE            0xe1000000 /* Start of LBC Registers */
 159 #ifdef CONFIG_PHYS_64BIT
 160 #define CONFIG_SYS_LBC1_BASE_PHYS       0xfe1000000ull
 161 #else
 162 #define CONFIG_SYS_LBC1_BASE_PHYS       CONFIG_SYS_LBC1_BASE
 163 #endif
 164
 165 /* Set the local bus clock 1/16 of platform clock */
 166 #define CONFIG_SYS_LBC_LCRR             (LCRR_CLKDIV_16 | LCRR_EADC_1)
 167
 168 #define CONFIG_SYS_BR0_PRELIM \
 169 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
 170 #define CONFIG_SYS_BR1_PRELIM \
 171 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
 172
 173 #define CONFIG_SYS_OR0_PRELIM   0xfff00010
 174 #define CONFIG_SYS_OR1_PRELIM   0xfff00010
 175
 176
 177 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 178
 179 #if defined(CONFIG_RAMBOOT_PBL)
 180 #define CONFIG_SYS_RAMBOOT
 181 #endif
 182
 183 #define CONFIG_BOARD_EARLY_INIT_F
 184 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 185 #define CONFIG_MISC_INIT_R
 186
 187 #define CONFIG_HWCONFIG
 188
 189 /* define to use L1 as initial stack */
 190 #define CONFIG_L1_INIT_RAM
 191 #define CONFIG_SYS_INIT_RAM_LOCK
 192 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 193 #ifdef CONFIG_PHYS_64BIT
 194 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 195 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 196 /* The assembler doesn't like typecast */
 197 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 198         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 199           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 200 #else
 201 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 202 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 203 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 204 #endif
 205 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 206
 207 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 208 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 209
 210 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 211 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 212
 213 /* Serial Port - controlled on board with jumper J8
 214  * open - index 2
 215  * shorted - index 1
 216  */
 217 #define CONFIG_CONS_INDEX       1
 218 #define CONFIG_SYS_NS16550
 219 #define CONFIG_SYS_NS16550_SERIAL
 220 #define CONFIG_SYS_NS16550_REG_SIZE     1
 221 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 222
 223 #define CONFIG_SYS_BAUDRATE_TABLE       \
 224 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 225
 226 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 227 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 228 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 229 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 230
 231 /* Use the HUSH parser */
 232 #define CONFIG_SYS_HUSH_PARSER
 233 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 234
 235 /* pass open firmware flat tree */
 236 #define CONFIG_OF_LIBFDT
 237 #define CONFIG_OF_BOARD_SETUP
 238
 239 /* new uImage format support */
 240 #define CONFIG_FIT
 241 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 242
 243 /* I2C */
 244 #define CONFIG_SYS_I2C
 245 #define CONFIG_SYS_I2C_FSL
 246 #define CONFIG_I2C_MULTI_BUS
 247 #define CONFIG_I2C_CMD_TREE
 248 #define CONFIG_SYS_FSL_I2C_SPEED                400000  /* I2C speed and slave address */
 249 #define CONFIG_SYS_FSL_I2C_SLAVE                0x7F
 250 #define CONFIG_SYS_FSL_I2C_OFFSET               0x118000
 251 #define CONFIG_SYS_FSL_I2C2_SPEED               400000  /* I2C speed and slave address */
 252 #define CONFIG_SYS_FSL_I2C2_SLAVE               0x7F
 253 #define CONFIG_SYS_FSL_I2C2_OFFSET              0x118100
 254 #define CONFIG_SYS_FSL_I2C3_SPEED               400000  /* I2C speed and slave address */
 255 #define CONFIG_SYS_FSL_I2C3_SLAVE               0x7F
 256 #define CONFIG_SYS_FSL_I2C3_OFFSET              0x119000
 257 #define CONFIG_SYS_FSL_I2C4_SPEED               400000  /* I2C speed and slave address */
 258 #define CONFIG_SYS_FSL_I2C4_SLAVE               0x7F
 259 #define CONFIG_SYS_FSL_I2C4_OFFSET              0x119100
 260
 261 #define CONFIG_ID_EEPROM
 262 #define CONFIG_SYS_I2C_EEPROM_NXID
 263 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 264 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 265 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 266
 267 #define CONFIG_SYS_I2C_GENERIC_MAC
 268 #define CONFIG_SYS_I2C_MAC1_BUS 3
 269 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
 270 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
 271 #define CONFIG_SYS_I2C_MAC2_BUS 0
 272 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
 273 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
 274
 275 #define CONFIG_CMD_DATE                 1
 276 #define CONFIG_RTC_MCP79411             1
 277 #define CONFIG_SYS_RTC_BUS_NUM          3
 278 #define CONFIG_SYS_I2C_RTC_ADDR         0x6f
 279
 280 /*
 281  * eSPI - Enhanced SPI
 282  */
 283 #define CONFIG_FSL_ESPI
 284
 285 /*
 286  * General PCI
 287  * Memory space is mapped 1-1, but I/O space must start from 0.
 288  */
 289
 290 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 291 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 292 #ifdef CONFIG_PHYS_64BIT
 293 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 294 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 295 #else
 296 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 297 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 298 #endif
 299 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 300 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 301 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 302 #ifdef CONFIG_PHYS_64BIT
 303 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 304 #else
 305 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 306 #endif
 307 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 308
 309 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 310 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 311 #ifdef CONFIG_PHYS_64BIT
 312 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 313 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 314 #else
 315 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 316 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 317 #endif
 318 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 319 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 320 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 321 #ifdef CONFIG_PHYS_64BIT
 322 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 323 #else
 324 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 325 #endif
 326 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 327
 328 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 329 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 330 #ifdef CONFIG_PHYS_64BIT
 331 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 332 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 333 #else
 334 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 335 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 336 #endif
 337 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 338 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 339 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 340 #ifdef CONFIG_PHYS_64BIT
 341 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 342 #else
 343 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 344 #endif
 345 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 346
 347 /* controller 4, Base address 203000 */
 348 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 349 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 350 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 351 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 352 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 353 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 354
 355 /* Qman/Bman */
 356 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 357 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 358 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 359 #ifdef CONFIG_PHYS_64BIT
 360 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 361 #else
 362 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 363 #endif
 364 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 365 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 366 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 367 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 368 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 369 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 370                                          CONFIG_SYS_BMAN_CENA_SIZE)
 371 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 372 #define CONFIG_SYS_BMAN_SWP_ISDR_REG   0xE08
 373 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 374 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 375 #ifdef CONFIG_PHYS_64BIT
 376 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 377 #else
 378 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 379 #endif
 380 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 381 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 382 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 383 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 384 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 385 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 386                                           CONFIG_SYS_QMAN_CENA_SIZE)
 387 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 388 #define CONFIG_SYS_QMAN_SWP_ISDR_REG   0xE08
 389
 390 #define CONFIG_SYS_DPAA_FMAN
 391 /* Default address of microcode for the Linux Fman driver */
 392 /*
 393  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 394  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 395  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 396  */
 397 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 398 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 399
 400 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 401 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 402
 403 #ifdef CONFIG_SYS_DPAA_FMAN
 404 #define CONFIG_FMAN_ENET
 405 #define CONFIG_PHY_MICREL
 406 #define CONFIG_PHY_MICREL_KSZ9021
 407 #endif
 408
 409 #ifdef CONFIG_PCI
 410 #define CONFIG_PCI_INDIRECT_BRIDGE
 411 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 412 #define CONFIG_NET_MULTI
 413
 414 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 415 #define CONFIG_DOS_PARTITION
 416 #endif  /* CONFIG_PCI */
 417
 418 /* SATA */
 419 #ifdef CONFIG_FSL_SATA_V2
 420 #define CONFIG_LIBATA
 421 #define CONFIG_FSL_SATA
 422
 423 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 424 #define CONFIG_SATA1
 425 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 426 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 427 #define CONFIG_SATA2
 428 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 429 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 430
 431 #define CONFIG_LBA48
 432 #define CONFIG_CMD_SATA
 433 #define CONFIG_DOS_PARTITION
 434 #define CONFIG_CMD_EXT2
 435 #endif
 436
 437 #ifdef CONFIG_FMAN_ENET
 438 #define CONFIG_SYS_TBIPA_VALUE  8
 439 #define CONFIG_MII              /* MII PHY management */
 440 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 441 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 442 #endif
 443
 444 /*
 445  * Environment
 446  */
 447 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 448 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 449
 450 /*
 451  * Command line configuration.
 452  */
 453 #define CONFIG_CMD_DHCP
 454 #define CONFIG_CMD_ERRATA
 455 #define CONFIG_CMD_GREPENV
 456 #define CONFIG_CMD_IRQ
 457 #define CONFIG_CMD_I2C
 458 #define CONFIG_CMD_MII
 459 #define CONFIG_CMD_PING
 460 #define CONFIG_CMD_REGINFO
 461
 462 #ifdef CONFIG_PCI
 463 #define CONFIG_CMD_PCI
 464 #endif
 465
 466 /*
 467  * USB
 468  */
 469 #define CONFIG_HAS_FSL_DR_USB
 470 #define CONFIG_HAS_FSL_MPH_USB
 471
 472 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 473 #define CONFIG_CMD_USB
 474 #define CONFIG_USB_STORAGE
 475 #define CONFIG_USB_EHCI
 476 #define CONFIG_USB_EHCI_FSL
 477 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 478 #define CONFIG_CMD_EXT2
 479 #define CONFIG_EHCI_IS_TDI
 480 #define CONFIG_USB_KEYBOARD
 481 #define CONFIG_SYS_USB_EVENT_POLL
 482  /* _VIA_CONTROL_EP  */
 483 #define CONFIG_CONSOLE_MUX
 484 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 485 #endif
 486
 487 #ifdef CONFIG_MMC
 488 #define CONFIG_FSL_ESDHC
 489 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 490 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 491 #define CONFIG_CMD_MMC
 492 #define CONFIG_GENERIC_MMC
 493 #define CONFIG_CMD_EXT2
 494 #define CONFIG_CMD_FAT
 495 #define CONFIG_DOS_PARTITION
 496 #endif
 497
 498 /*
 499  * Miscellaneous configurable options
 500  */
 501 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 502 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 503 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 504 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 505 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 506 #ifdef CONFIG_CMD_KGDB
 507 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 508 #else
 509 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 510 #endif
 511 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 512 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 513 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 514
 515 /*
 516  * For booting Linux, the board info and command line data
 517  * have to be in the first 64 MB of memory, since this is
 518  * the maximum mapped by the Linux kernel during initialization.
 519  */
 520 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 521 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 522
 523 #ifdef CONFIG_CMD_KGDB
 524 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 525 #endif
 526
 527 /*
 528  * Environment Configuration
 529  */
 530 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 531 #define CONFIG_BOOTFILE         "uImage"
 532 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 533
 534 /* default location for tftp and bootm */
 535 #define CONFIG_LOADADDR         1000000
 536
 537 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 538
 539 #define CONFIG_BAUDRATE 115200
 540
 541 #define __USB_PHY_TYPE  utmi
 542
 543 #define CONFIG_EXTRA_ENV_SETTINGS \
 544 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 545 "bank_intlv=cs0_cs1;"                                   \
 546 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 547 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 548 "netdev=eth0\0"                                         \
 549 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 550 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
 551 "consoledev=ttyS0\0"                                    \
 552 "ramdiskaddr=2000000\0"                                 \
 553 "fdtaddr=c00000\0"                                      \
 554 "bdev=sda3\0"
 555
 556 #define CONFIG_HDBOOT                                   \
 557 "setenv bootargs root=/dev/$bdev rw "           \
 558 "console=$consoledev,$baudrate $othbootargs;"   \
 559 "tftp $loadaddr $bootfile;"                     \
 560 "tftp $fdtaddr $fdtfile;"                       \
 561 "bootm $loadaddr - $fdtaddr"
 562
 563 #define CONFIG_NFSBOOTCOMMAND                   \
 564 "setenv bootargs root=/dev/nfs rw "     \
 565 "nfsroot=$serverip:$rootpath "          \
 566 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 567 "console=$consoledev,$baudrate $othbootargs;"   \
 568 "tftp $loadaddr $bootfile;"             \
 569 "tftp $fdtaddr $fdtfile;"               \
 570 "bootm $loadaddr - $fdtaddr"
 571
 572 #define CONFIG_RAMBOOTCOMMAND                           \
 573 "setenv bootargs root=/dev/ram rw "             \
 574 "console=$consoledev,$baudrate $othbootargs;"   \
 575 "tftp $ramdiskaddr $ramdiskfile;"               \
 576 "tftp $loadaddr $bootfile;"                     \
 577 "tftp $fdtaddr $fdtfile;"                       \
 578 "bootm $loadaddr $ramdiskaddr $fdtaddr"
 579
 580 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 581
 582 #include <asm/fsl_secure_boot.h>
 583
 584 #ifdef CONFIG_SECURE_BOOT
 585 #endif
 586
 587 #endif  /* __CONFIG_H */