include/configs/da850evm.h

   1 /*
   2  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * Based on davinci_dvevm.h. Original Copyrights follow:
   5  *
   6  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * Board
  16  */
  17 #define CONFIG_DRIVER_TI_EMAC
  18 /* check if direct NOR boot config is used */
  19 #ifndef CONFIG_DIRECT_NOR_BOOT
  20 #define CONFIG_USE_SPIFLASH
  21 #endif
  22
  23 /*
  24 * Disable DM_* for SPL build and can be re-enabled after adding
  25 * DM support in SPL
  26 */
  27 #ifdef CONFIG_SPL_BUILD
  28 #undef CONFIG_DM_SPI
  29 #undef CONFIG_DM_SPI_FLASH
  30 #undef CONFIG_DM_I2C
  31 #undef CONFIG_DM_I2C_COMPAT
  32 #endif
  33 /*
  34  * SoC Configuration
  35  */
  36 #define CONFIG_MACH_DAVINCI_DA850_EVM
  37 #define CONFIG_SOC_DA8XX                /* TI DA8xx SoC */
  38 #define CONFIG_SOC_DA850                /* TI DA850 SoC */
  39 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  40 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  41 #define CONFIG_SYS_OSCIN_FREQ           24000000
  42 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  43 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  44
  45 #ifdef CONFIG_DIRECT_NOR_BOOT
  46 #define CONFIG_ARCH_CPU_INIT
  47 #define CONFIG_DA8XX_GPIO
  48 #define CONFIG_SYS_TEXT_BASE            0x60000000
  49 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
  50 #define CONFIG_DA850_LOWLEVEL
  51 #else
  52 #define CONFIG_SYS_TEXT_BASE            0xc1080000
  53 #endif
  54
  55 /*
  56  * Memory Info
  57  */
  58 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
  59 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  60 #define PHYS_SDRAM_1_SIZE       (64 << 20) /* SDRAM size 64MB */
  61 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  62
  63 /* memtest start addr */
  64 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
  65
  66 /* memtest will be run on 16MB */
  67 #define CONFIG_SYS_MEMTEST_END  (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
  68
  69 #define CONFIG_NR_DRAM_BANKS    1 /* we have 1 bank of DRAM */
  70
  71 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  72         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  73         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
  74         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
  75         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
  76         DAVINCI_SYSCFG_SUSPSRC_I2C)
  77
  78 /*
  79  * PLL configuration
  80  */
  81 #define CONFIG_SYS_DV_CLKMODE          0
  82 #define CONFIG_SYS_DA850_PLL0_POSTDIV  1
  83 #define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
  84 #define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
  85 #define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
  86 #define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
  87 #define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
  88 #define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
  89 #define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
  90
  91 #define CONFIG_SYS_DA850_PLL1_POSTDIV  1
  92 #define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
  93 #define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
  94 #define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8002
  95
  96 #define CONFIG_SYS_DA850_PLL0_PLLM     24
  97 #define CONFIG_SYS_DA850_PLL1_PLLM     21
  98
  99 /*
 100  * DDR2 memory configuration
 101  */
 102 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
 103                                         DV_DDR_PHY_EXT_STRBEN | \
 104                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
 105
 106 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
 107         (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |     \
 108         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
 109         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
 110         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
 111         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
 112         (0x2 << DV_DDR_SDCR_IBANK_SHIFT) |      \
 113         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
 114
 115 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
 116 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
 117
 118 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
 119         (14 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
 120         (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
 121         (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
 122         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
 123         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
 124         (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
 125         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
 126         (0 << DV_DDR_SDTMR1_WTR_SHIFT))
 127
 128 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
 129         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
 130         (0 << DV_DDR_SDTMR2_XP_SHIFT) |         \
 131         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
 132         (17 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
 133         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
 134         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
 135         (0 << DV_DDR_SDTMR2_CKE_SHIFT))
 136
 137 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
 138 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
 139
 140 /*
 141  * Serial Driver info
 142  */
 143
 144 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DIRECT_NOR_BOOT)
 145 #define CONFIG_SYS_NS16550_SERIAL
 146 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
 147 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
 148 #endif
 149 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 150 #define CONFIG_CONS_INDEX       1               /* use UART0 for console */
 151
 152 #define CONFIG_SPI
 153 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
 154 #ifdef CONFIG_SPL_BUILD
 155 #define CONFIG_SYS_SPI_BASE             DAVINCI_SPI1_BASE
 156 #define CONFIG_SF_DEFAULT_SPEED         30000000
 157 #define CONFIG_ENV_SPI_MAX_HZ   CONFIG_SF_DEFAULT_SPEED
 158 #endif
 159
 160 #ifdef CONFIG_USE_SPIFLASH
 161 #define CONFIG_SPL_SPI_LOAD
 162 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x8000
 163 #define CONFIG_SYS_SPI_U_BOOT_SIZE      0x40000
 164 #endif
 165
 166 /*
 167  * I2C Configuration
 168  */
 169 #ifndef CONFIG_SPL_BUILD
 170 #define CONFIG_SYS_I2C_DAVINCI
 171 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
 172 #endif
 173
 174 /*
 175  * Flash & Environment
 176  */
 177 #ifdef CONFIG_USE_NAND
 178 #define CONFIG_NAND_DAVINCI
 179 #define CONFIG_ENV_OFFSET               0x0 /* Block 0--not used by bootcode */
 180 #define CONFIG_ENV_SIZE                 (128 << 10)
 181 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 182 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 183 #define CONFIG_SYS_NAND_PAGE_2K
 184 #define CONFIG_SYS_NAND_CS              3
 185 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 186 #define CONFIG_SYS_NAND_MASK_CLE                0x10
 187 #define CONFIG_SYS_NAND_MASK_ALE                0x8
 188 #undef CONFIG_SYS_NAND_HW_ECC
 189 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 190 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 191 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 192 #define CONFIG_SYS_NAND_PAGE_SIZE       (2 << 10)
 193 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
 194 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x28000
 195 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x60000
 196 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
 197 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 198 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
 199                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
 200                                         CONFIG_SYS_MALLOC_LEN -       \
 201                                         GENERATED_GBL_DATA_SIZE)
 202 #define CONFIG_SYS_NAND_ECCPOS          {                               \
 203                                 24, 25, 26, 27, 28, \
 204                                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
 205                                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
 206                                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
 207                                 59, 60, 61, 62, 63 }
 208 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 209 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 210 #define CONFIG_SYS_NAND_ECCSIZE         512
 211 #define CONFIG_SYS_NAND_ECCBYTES        10
 212 #define CONFIG_SYS_NAND_OOBSIZE         64
 213 #define CONFIG_SPL_NAND_BASE
 214 #define CONFIG_SPL_NAND_DRIVERS
 215 #define CONFIG_SPL_NAND_ECC
 216 #define CONFIG_SPL_NAND_LOAD
 217 #endif
 218
 219 /*
 220  * Network & Ethernet Configuration
 221  */
 222 #ifdef CONFIG_DRIVER_TI_EMAC
 223 #define CONFIG_MII
 224 #define CONFIG_BOOTP_DNS
 225 #define CONFIG_BOOTP_DNS2
 226 #define CONFIG_BOOTP_SEND_HOSTNAME
 227 #define CONFIG_NET_RETRY_COUNT  10
 228 #endif
 229
 230 #ifdef CONFIG_USE_NOR
 231 #define CONFIG_FLASH_CFI_DRIVER
 232 #define CONFIG_SYS_FLASH_CFI
 233 #define CONFIG_SYS_FLASH_PROTECTION
 234 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* max number of flash banks */
 235 #define CONFIG_SYS_FLASH_SECT_SZ        (128 << 10) /* 128KB */
 236 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_FLASH_SECT_SZ * 3)
 237 #define CONFIG_ENV_SIZE                 (10 << 10) /* 10KB */
 238 #define CONFIG_SYS_FLASH_BASE           DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 239 #define PHYS_FLASH_SIZE                 (8 << 20) /* Flash size 8MB */
 240 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
 241                + 3)
 242 #define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_FLASH_SECT_SZ
 243 #endif
 244
 245 #ifdef CONFIG_USE_SPIFLASH
 246 #define CONFIG_ENV_SIZE                 (64 << 10)
 247 #define CONFIG_ENV_OFFSET               (512 << 10)
 248 #define CONFIG_ENV_SECT_SIZE            (64 << 10)
 249 #ifdef CONFIG_SPL_BUILD
 250 #undef CONFIG_SPI_FLASH_MTD
 251 #endif
 252 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 253 #define CONFIG_MTD_PARTITIONS           /* required for UBI partition support */
 254 #endif
 255
 256 /*
 257  * U-Boot general configuration
 258  */
 259 #define CONFIG_MISC_INIT_R
 260 #define CONFIG_BOOTFILE         "uImage" /* Boot file name */
 261 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 262 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 263 #define CONFIG_SYS_LOAD_ADDR    (PHYS_SDRAM_1 + 0x700000)
 264 #define CONFIG_AUTO_COMPLETE
 265 #define CONFIG_CMDLINE_EDITING
 266 #define CONFIG_SYS_LONGHELP
 267 #define CONFIG_MX_CYCLIC
 268
 269 /*
 270  * Linux Information
 271  */
 272 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 273 #define CONFIG_HWCONFIG         /* enable hwconfig */
 274 #define CONFIG_CMDLINE_TAG
 275 #define CONFIG_REVISION_TAG
 276 #define CONFIG_SETUP_MEMORY_TAGS
 277
 278 #define CONFIG_BOOTCOMMAND \
 279                 "run envboot; " \
 280                 "run mmcboot; "
 281
 282 #define DEFAULT_LINUX_BOOT_ENV \
 283         "loadaddr=0xc0700000\0" \
 284         "fdtaddr=0xc0600000\0" \
 285         "scriptaddr=0xc0600000\0"
 286
 287 #include <environment/ti/mmc.h>
 288
 289 #define CONFIG_EXTRA_ENV_SETTINGS \
 290         DEFAULT_LINUX_BOOT_ENV \
 291         DEFAULT_MMC_TI_ARGS \
 292         "bootpart=0:2\0" \
 293         "bootdir=/boot\0" \
 294         "bootfile=zImage\0" \
 295         "fdtfile=da850-evm.dtb\0" \
 296         "boot_fdt=yes\0" \
 297         "boot_fit=0\0" \
 298         "console=ttyS2,115200n8\0" \
 299         "hwconfig=dsp:wake=yes"
 300
 301 #ifdef CONFIG_CMD_BDI
 302 #define CONFIG_CLOCKS
 303 #endif
 304
 305 #ifdef CONFIG_USE_NAND
 306 #define CONFIG_MTD_DEVICE
 307 #define CONFIG_MTD_PARTITIONS
 308 #endif
 309
 310 #if !defined(CONFIG_USE_NAND) && \
 311         !defined(CONFIG_USE_NOR) && \
 312         !defined(CONFIG_USE_SPIFLASH)
 313 #define CONFIG_ENV_SIZE         (16 << 10)
 314 #endif
 315
 316 #ifndef CONFIG_DIRECT_NOR_BOOT
 317 /* defines for SPL */
 318 #define CONFIG_SPL_FRAMEWORK
 319 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
 320                                                 CONFIG_SYS_MALLOC_LEN)
 321 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
 322 #define CONFIG_SPL_SPI_LOAD
 323 #define CONFIG_SPL_STACK        0x8001ff00
 324 #define CONFIG_SPL_TEXT_BASE    0x80000000
 325 #define CONFIG_SPL_MAX_FOOTPRINT        32768
 326 #define CONFIG_SPL_PAD_TO       32768
 327 #endif
 328
 329 /* Load U-Boot Image From MMC */
 330 #ifdef CONFIG_SPL_MMC_LOAD
 331 #undef CONFIG_SPL_SPI_LOAD
 332 #endif
 333
 334 /* additions for new relocation code, must added to all boards */
 335 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 336
 337 #ifdef CONFIG_DIRECT_NOR_BOOT
 338 #define CONFIG_SYS_INIT_SP_ADDR         0x8001ff00
 339 #else
 340 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
 341                                         GENERATED_GBL_DATA_SIZE)
 342 #endif /* CONFIG_DIRECT_NOR_BOOT */
 343
 344 #include <asm/arch/hardware.h>
 345
 346 #endif /* __CONFIG_H */