include/configs/db-mv784mp-gp.h

   1 /*
   2  * Copyright (C) 2014 Stefan Roese <sr@denx.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _CONFIG_DB_MV7846MP_GP_H
   8 #define _CONFIG_DB_MV7846MP_GP_H
   9
  10 /*
  11  * High Level Configuration Options (easy to change)
  12  */
  13 #define CONFIG_ARMADA_XP                /* SOC Family Name */
  14 #define CONFIG_DB_784MP_GP              /* Board target name for DDR training */
  15
  16 #ifdef CONFIG_SPL_BUILD
  17 #define CONFIG_SKIP_LOWLEVEL_INIT       /* disable board lowlevel_init */
  18 #endif
  19 #define CONFIG_SYS_GENERIC_BOARD
  20 #define CONFIG_DISPLAY_BOARDINFO_LATE
  21
  22 /*
  23  * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  24  * for DDR ECC byte filling in the SPL before loading the main
  25  * U-Boot into it.
  26  */
  27 #define CONFIG_SYS_TEXT_BASE    0x00800000
  28 #define CONFIG_SYS_TCLK         250000000       /* 250MHz */
  29
  30 /*
  31  * Commands configuration
  32  */
  33 #define CONFIG_SYS_NO_FLASH             /* Declare no flash (NOR/SPI) */
  34 #define CONFIG_CMD_DHCP
  35 #define CONFIG_CMD_ENV
  36 #define CONFIG_CMD_I2C
  37 #define CONFIG_CMD_IDE
  38 #define CONFIG_CMD_NAND
  39 #define CONFIG_CMD_PCI
  40 #define CONFIG_CMD_PING
  41 #define CONFIG_CMD_SF
  42 #define CONFIG_CMD_SPI
  43 #define CONFIG_CMD_TFTPPUT
  44 #define CONFIG_CMD_TIME
  45 #define CONFIG_CMD_USB
  46
  47 /* I2C */
  48 #define CONFIG_SYS_I2C
  49 #define CONFIG_SYS_I2C_MVTWSI
  50 #define CONFIG_I2C_MVTWSI_BASE0         MVEBU_TWSI_BASE
  51 #define CONFIG_SYS_I2C_SLAVE            0x0
  52 #define CONFIG_SYS_I2C_SPEED            100000
  53
  54 /* USB/EHCI configuration */
  55 #define CONFIG_USB_EHCI
  56 #define CONFIG_USB_STORAGE
  57 #define CONFIG_USB_EHCI_MARVELL
  58 #define CONFIG_EHCI_IS_TDI
  59 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
  60
  61 /* SPI NOR flash default params, used by sf commands */
  62 #define CONFIG_SF_DEFAULT_SPEED         1000000
  63 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_3
  64 #define CONFIG_SPI_FLASH_STMICRO
  65
  66 /* Environment in SPI NOR flash */
  67 #define CONFIG_ENV_IS_IN_SPI_FLASH
  68 #define CONFIG_ENV_OFFSET               (1 << 20) /* 1MiB in */
  69 #define CONFIG_ENV_SIZE                 (64 << 10) /* 64KiB */
  70 #define CONFIG_ENV_SECT_SIZE            (64 << 10) /* 64KiB sectors */
  71
  72 #define CONFIG_PHY_MARVELL              /* there is a marvell phy */
  73 #define CONFIG_PHY_ADDR                 { 0x10, 0x11, 0x12, 0x13 }
  74 #define CONFIG_SYS_NETA_INTERFACE_TYPE  PHY_INTERFACE_MODE_QSGMII
  75 #define PHY_ANEG_TIMEOUT        8000    /* PHY needs a longer aneg time */
  76 #define CONFIG_RESET_PHY_R
  77
  78 #define CONFIG_SYS_CONSOLE_INFO_QUIET   /* don't print console @ startup */
  79 #define CONFIG_SYS_ALT_MEMTEST
  80
  81 /* SATA support */
  82 #ifdef CONFIG_CMD_IDE
  83 #define __io
  84 #define CONFIG_IDE_PREINIT
  85 #define CONFIG_MVSATA_IDE
  86
  87 /* Needs byte-swapping for ATA data register */
  88 #define CONFIG_IDE_SWAP_IO
  89
  90 #define CONFIG_SYS_ATA_REG_OFFSET       0x0100 /* Offset for register access */
  91 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0100 /* Offset for data I/O */
  92 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
  93
  94 /* Each 8-bit ATA register is aligned to a 4-bytes address */
  95 #define CONFIG_SYS_ATA_STRIDE           4
  96
  97 /* CONFIG_CMD_IDE requires some #defines for ATA registers */
  98 #define CONFIG_SYS_IDE_MAXBUS           2
  99 #define CONFIG_SYS_IDE_MAXDEVICE        CONFIG_SYS_IDE_MAXBUS
 100
 101 /* ATA registers base is at SATA controller base */
 102 #define CONFIG_SYS_ATA_BASE_ADDR        MVEBU_AXP_SATA_BASE
 103 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x2000
 104 #define CONFIG_SYS_ATA_IDE1_OFFSET      0x4000
 105
 106 #define CONFIG_DOS_PARTITION
 107 #endif /* CONFIG_CMD_IDE */
 108
 109 /* PCIe support */
 110 #define CONFIG_PCI
 111 #define CONFIG_PCI_MVEBU
 112 #define CONFIG_PCI_PNP
 113 #define CONFIG_PCI_SCAN_SHOW
 114 #define CONFIG_E1000    /* enable Intel E1000 support for testing */
 115
 116 /* NAND */
 117 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 118 #define CONFIG_SYS_NAND_ONFI_DETECTION
 119
 120 /*
 121  * mv-common.h should be defined after CMD configs since it used them
 122  * to enable certain macros
 123  */
 124 #include "mv-common.h"
 125
 126 /*
 127  * Memory layout while starting into the bin_hdr via the
 128  * BootROM:
 129  *
 130  * 0x4000.4000 - 0x4003.4000    headers space (192KiB)
 131  * 0x4000.4030                  bin_hdr start address
 132  * 0x4003.4000 - 0x4004.7c00    BootROM memory allocations (15KiB)
 133  * 0x4007.fffc                  BootROM stack top
 134  *
 135  * The address space between 0x4007.fffc and 0x400f.fff is not locked in
 136  * L2 cache thus cannot be used.
 137  */
 138
 139 /* SPL */
 140 /* Defines for SPL */
 141 #define CONFIG_SPL_FRAMEWORK
 142 #define CONFIG_SPL_TEXT_BASE            0x40004030
 143 #define CONFIG_SPL_MAX_SIZE             ((128 << 10) - 0x4030)
 144
 145 #define CONFIG_SPL_BSS_START_ADDR       (0x40000000 + (128 << 10))
 146 #define CONFIG_SPL_BSS_MAX_SIZE         (16 << 10)
 147
 148 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
 149                                          CONFIG_SPL_BSS_MAX_SIZE)
 150 #define CONFIG_SYS_SPL_MALLOC_SIZE      (16 << 10)
 151
 152 #define CONFIG_SPL_STACK                (0x40000000 + ((192 - 16) << 10))
 153 #define CONFIG_SPL_BOOTROM_SAVE         (CONFIG_SPL_STACK + 4)
 154
 155 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 156 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 157 #define CONFIG_SPL_SERIAL_SUPPORT
 158 #define CONFIG_SPL_I2C_SUPPORT
 159
 160 /* SPL related SPI defines */
 161 #define CONFIG_SPL_SPI_SUPPORT
 162 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 163 #define CONFIG_SPL_SPI_LOAD
 164 #define CONFIG_SPL_SPI_BUS              0
 165 #define CONFIG_SPL_SPI_CS               0
 166 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x20000
 167 #define CONFIG_SYS_U_BOOT_OFFS          CONFIG_SYS_SPI_U_BOOT_OFFS
 168
 169 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
 170 #define CONFIG_SYS_MVEBU_DDR_AXP
 171 #define CONFIG_SPD_EEPROM               0x4e
 172
 173 #endif /* _CONFIG_DB_MV7846MP_GP_H */