include/configs/db-mv784mp-gp.h

   1 /*
   2  * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _CONFIG_DB_MV7846MP_GP_H
   8 #define _CONFIG_DB_MV7846MP_GP_H
   9
  10 /*
  11  * High Level Configuration Options (easy to change)
  12  */
  13 #define CONFIG_ARMADA_XP                /* SOC Family Name */
  14 #define CONFIG_DB_784MP_GP              /* Board target name for DDR training */
  15
  16 #define CONFIG_DISPLAY_BOARDINFO_LATE
  17
  18 /*
  19  * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  20  * for DDR ECC byte filling in the SPL before loading the main
  21  * U-Boot into it.
  22  */
  23 #define CONFIG_SYS_TEXT_BASE    0x00800000
  24 #define CONFIG_SYS_TCLK         250000000       /* 250MHz */
  25
  26 /*
  27  * Commands configuration
  28  */
  29 #define CONFIG_SYS_NO_FLASH             /* Declare no flash (NOR/SPI) */
  30 #define CONFIG_CMD_CACHE
  31 #define CONFIG_CMD_DHCP
  32 #define CONFIG_CMD_ENV
  33 #define CONFIG_CMD_EXT2
  34 #define CONFIG_CMD_EXT4
  35 #define CONFIG_CMD_FAT
  36 #define CONFIG_CMD_FS_GENERIC
  37 #define CONFIG_CMD_I2C
  38 #define CONFIG_CMD_NAND
  39 #define CONFIG_CMD_PCI
  40 #define CONFIG_CMD_PING
  41 #define CONFIG_CMD_SATA
  42 #define CONFIG_CMD_SF
  43 #define CONFIG_CMD_SPI
  44 #define CONFIG_CMD_TFTPPUT
  45 #define CONFIG_CMD_TIME
  46
  47 /* I2C */
  48 #define CONFIG_SYS_I2C
  49 #define CONFIG_SYS_I2C_MVTWSI
  50 #define CONFIG_I2C_MVTWSI_BASE0         MVEBU_TWSI_BASE
  51 #define CONFIG_SYS_I2C_SLAVE            0x0
  52 #define CONFIG_SYS_I2C_SPEED            100000
  53
  54 /* USB/EHCI configuration */
  55 #define CONFIG_EHCI_IS_TDI
  56 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
  57
  58 /* SPI NOR flash default params, used by sf commands */
  59 #define CONFIG_SF_DEFAULT_SPEED         1000000
  60 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_3
  61
  62 /* Environment in SPI NOR flash */
  63 #define CONFIG_ENV_IS_IN_SPI_FLASH
  64 #define CONFIG_ENV_OFFSET               (1 << 20) /* 1MiB in */
  65 #define CONFIG_ENV_SIZE                 (64 << 10) /* 64KiB */
  66 #define CONFIG_ENV_SECT_SIZE            (64 << 10) /* 64KiB sectors */
  67
  68 #define CONFIG_PHY_MARVELL              /* there is a marvell phy */
  69 #define PHY_ANEG_TIMEOUT        8000    /* PHY needs a longer aneg time */
  70
  71 #define CONFIG_SYS_CONSOLE_INFO_QUIET   /* don't print console @ startup */
  72 #define CONFIG_SYS_ALT_MEMTEST
  73
  74 /* SATA support */
  75 #define CONFIG_SYS_SATA_MAX_DEVICE      2
  76 #define CONFIG_SATA_MV
  77 #define CONFIG_LIBATA
  78 #define CONFIG_LBA48
  79 #define CONFIG_EFI_PARTITION
  80 #define CONFIG_DOS_PARTITION
  81
  82 /* Additional FS support/configuration */
  83 #define CONFIG_SUPPORT_VFAT
  84
  85 /* PCIe support */
  86 #ifndef CONFIG_SPL_BUILD
  87 #define CONFIG_PCI
  88 #define CONFIG_PCI_MVEBU
  89 #define CONFIG_PCI_PNP
  90 #define CONFIG_PCI_SCAN_SHOW
  91 #endif
  92
  93 /* NAND */
  94 #define CONFIG_SYS_NAND_USE_FLASH_BBT
  95 #define CONFIG_SYS_NAND_ONFI_DETECTION
  96
  97 /*
  98  * mv-common.h should be defined after CMD configs since it used them
  99  * to enable certain macros
 100  */
 101 #include "mv-common.h"
 102
 103 /*
 104  * Memory layout while starting into the bin_hdr via the
 105  * BootROM:
 106  *
 107  * 0x4000.4000 - 0x4003.4000    headers space (192KiB)
 108  * 0x4000.4030                  bin_hdr start address
 109  * 0x4003.4000 - 0x4004.7c00    BootROM memory allocations (15KiB)
 110  * 0x4007.fffc                  BootROM stack top
 111  *
 112  * The address space between 0x4007.fffc and 0x400f.fff is not locked in
 113  * L2 cache thus cannot be used.
 114  */
 115
 116 /* SPL */
 117 /* Defines for SPL */
 118 #define CONFIG_SPL_FRAMEWORK
 119 #define CONFIG_SPL_TEXT_BASE            0x40004030
 120 #define CONFIG_SPL_MAX_SIZE             ((128 << 10) - 0x4030)
 121
 122 #define CONFIG_SPL_BSS_START_ADDR       (0x40000000 + (128 << 10))
 123 #define CONFIG_SPL_BSS_MAX_SIZE         (16 << 10)
 124
 125 #ifdef CONFIG_SPL_BUILD
 126 #define CONFIG_SYS_MALLOC_SIMPLE
 127 #endif
 128
 129 #define CONFIG_SPL_STACK                (0x40000000 + ((192 - 16) << 10))
 130 #define CONFIG_SPL_BOOTROM_SAVE         (CONFIG_SPL_STACK + 4)
 131
 132 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 133 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 134 #define CONFIG_SPL_SERIAL_SUPPORT
 135 #define CONFIG_SPL_I2C_SUPPORT
 136
 137 /* SPL related SPI defines */
 138 #define CONFIG_SPL_SPI_SUPPORT
 139 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 140 #define CONFIG_SPL_SPI_LOAD
 141 #define CONFIG_SPL_SPI_BUS              0
 142 #define CONFIG_SPL_SPI_CS               0
 143 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x20000
 144 #define CONFIG_SYS_U_BOOT_OFFS          CONFIG_SYS_SPI_U_BOOT_OFFS
 145
 146 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
 147 #define CONFIG_SYS_MVEBU_DDR_AXP
 148 #define CONFIG_SPD_EEPROM               0x4e
 149 #define CONFIG_BOARD_ECC_SUPPORT        /* this board supports ECC */
 150
 151 #endif /* _CONFIG_DB_MV7846MP_GP_H */