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common: bootdelay: move CONFIG_BOOTDELAY into a Kconfig option
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1 /*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 /*
9 * This file contains the configuration parameters for the dbau1x00 board.
10 */
11
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14
15 #define CONFIG_DBAU1X00 1
16 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
17
18 #define CONFIG_DISPLAY_BOARDINFO
19
20 #ifdef CONFIG_DBAU1000
21 /* Also known as Merlot */
22 #define CONFIG_SOC_AU1000 1
23 #else
24 #ifdef CONFIG_DBAU1100
25 #define CONFIG_SOC_AU1100 1
26 #else
27 #ifdef CONFIG_DBAU1500
28 #define CONFIG_SOC_AU1500 1
29 #else
30 #ifdef CONFIG_DBAU1550
31 /* Cabernet */
32 #define CONFIG_SOC_AU1550 1
33 #else
34 #error "No valid board set"
35 #endif
36 #endif
37 #endif
38 #endif
39
40
41 #define CONFIG_BAUDRATE 115200
42
43 /* valid baudrates */
44
45 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
46 #undef CONFIG_BOOTARGS
47
48 #define CONFIG_EXTRA_ENV_SETTINGS \
49 "addmisc=setenv bootargs ${bootargs} " \
50 "console=ttyS0,${baudrate} " \
51 "panic=1\0" \
52 "bootfile=/tftpboot/vmlinux.srec\0" \
53 "load=tftp 80500000 ${u-boot}\0" \
54 ""
55
56 #ifdef CONFIG_DBAU1550
57 /* Boot from flash by default, revert to bootp */
58 #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
59 #else /* CONFIG_DBAU1550 */
60 #define CONFIG_BOOTCOMMAND "bootp;bootm"
61 #endif /* CONFIG_DBAU1550 */
62
63 /*
64 * BOOTP options
65 */
66 #define CONFIG_BOOTP_BOOTFILESIZE
67 #define CONFIG_BOOTP_BOOTPATH
68 #define CONFIG_BOOTP_GATEWAY
69 #define CONFIG_BOOTP_HOSTNAME
70
71 /*
72 * Command line configuration.
73 */
74 #undef CONFIG_CMD_BEDBUG
75
76 #ifdef CONFIG_DBAU1550
77
78 #undef CONFIG_CMD_IDE
79 #undef CONFIG_CMD_PCMCIA
80
81 #else
82
83 #define CONFIG_CMD_IDE
84
85 #endif
86
87 /*
88 * Miscellaneous configurable options
89 */
90 #define CONFIG_SYS_LONGHELP /* undef to save memory */
91
92 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
93 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
94 #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
95
96 #define CONFIG_SYS_MALLOC_LEN 128*1024
97
98 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
99
100 #define CONFIG_SYS_MHZ 396
101
102 #if (CONFIG_SYS_MHZ % 12) != 0
103 #error "Invalid CPU frequency - must be multiple of 12!"
104 #endif
105
106 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
107
108 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
109
110 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
111
112 #define CONFIG_SYS_MEMTEST_START 0x80100000
113 #define CONFIG_SYS_MEMTEST_END 0x80800000
114
115 /*-----------------------------------------------------------------------
116 * FLASH and environment organization
117 */
118 #ifdef CONFIG_DBAU1550
119
120 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
121 #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
122
123 #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
124 #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
125
126 #else /* CONFIG_DBAU1550 */
127
128 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
129 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
130
131 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
132 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
133
134 #endif /* CONFIG_DBAU1550 */
135
136 #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
137
138 #define CONFIG_SYS_FLASH_CFI 1
139 #define CONFIG_FLASH_CFI_DRIVER 1
140
141 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
142 #define CONFIG_SYS_MONITOR_LEN (192 << 10)
143
144 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
145
146 /* We boot from this flash, selected with dip switch */
147 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
148
149 /* timeout values are in ticks */
150 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
151 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
152
153 #define CONFIG_ENV_IS_NOWHERE 1
154
155 /* Address and size of Primary Environment Sector */
156 #define CONFIG_ENV_ADDR 0xB0030000
157 #define CONFIG_ENV_SIZE 0x10000
158
159 #define CONFIG_FLASH_16BIT
160
161 #define CONFIG_NR_DRAM_BANKS 2
162
163 #ifdef CONFIG_DBAU1550
164 #define MEM_SIZE 192
165 #else
166 #define MEM_SIZE 64
167 #endif
168
169 #define CONFIG_MEMSIZE_IN_BYTES
170
171 #ifndef CONFIG_DBAU1550
172 /*---ATA PCMCIA ------------------------------------*/
173 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
174 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
175 #define CONFIG_PCMCIA_SLOT_A
176
177 #define CONFIG_ATAPI 1
178 #define CONFIG_MAC_PARTITION 1
179
180 /* We run CF in "true ide" mode or a harddrive via pcmcia */
181 #define CONFIG_IDE_PCMCIA 1
182
183 /* We only support one slot for now */
184 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
185 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
186
187 #undef CONFIG_IDE_LED /* LED for ide not supported */
188 #undef CONFIG_IDE_RESET /* reset for ide not supported */
189
190 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
191
192 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
193
194 /* Offset for data I/O */
195 #define CONFIG_SYS_ATA_DATA_OFFSET 8
196
197 /* Offset for normal register accesses */
198 #define CONFIG_SYS_ATA_REG_OFFSET 0
199
200 /* Offset for alternate registers */
201 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
202 #endif /* CONFIG_DBAU1550 */
203
204 #endif /* __CONFIG_H */