include/configs/debris.h

   1 /*
   2  * (C) Copyright 2001, 2002
   3  * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* ------------------------------------------------------------------------- */
  25
  26 /*
  27  * board/config.h - configuration options, board specific
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /* Environments */
  34
  35 /* bootargs */
  36 #define CONFIG_BOOTARGS \
  37         "console=ttyS0,9600 init=/linuxrc " \
  38         "root=/dev/nfs rw nfsroot=192.168.0.1:" \
  39         "/tftpboot/target " \
  40         "ip=192.168.0.2:192.168.0.1:192.168.0.1:" \
  41         "255.255.255.0:debris:eth0:none " \
  42         "mtdparts=phys:12m(root),-(kernel)"
  43
  44 /* bootcmd */
  45 #define CONFIG_BOOTCOMMAND \
  46         "tftp 800000 pImage; " \
  47         "setenv bootargs console=ttyS0,9600 init=/linuxrc " \
  48         "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
  49         "ip=$(ipaddr):$(serverip):$(gatewayip):" \
  50         "$(netmask):$(hostname):eth0:none " \
  51         "mtdparts=phys:12m(root),-(kernel); " \
  52         "bootm 800000"
  53
  54 /* bootdelay */
  55 #define CONFIG_BOOTDELAY        5       /* autoboot 5s */
  56
  57 /* baudrate */
  58 #define CONFIG_BAUDRATE         9600    /* console baudrate = 9600bps   */
  59
  60 /* loads_echo */
  61 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
  62
  63 /* ethaddr */
  64 #undef CONFIG_ETHADDR
  65
  66 /* eth2addr */
  67 #undef CONFIG_ETH2ADDR
  68
  69 /* eth3addr */
  70 #undef CONFIG_ETH3ADDR
  71
  72 /* ipaddr */
  73 #define CONFIG_IPADDR   192.168.0.2
  74
  75 /* serverip */
  76 #define CONFIG_SERVERIP 192.168.0.1
  77
  78 /* autoload */
  79 #undef CFG_AUTOLOAD
  80
  81 /* rootpath */
  82 #define CONFIG_ROOTPATH /tftpboot/target
  83
  84 /* gatewayip */
  85 #define CONFIG_GATEWAYIP 192.168.0.1
  86
  87 /* netmask */
  88 #define CONFIG_NETMASK 255.255.255.0
  89
  90 /* hostname */
  91 #define CONFIG_HOSTNAME debris
  92
  93 /* bootfile */
  94 #define CONFIG_BOOTFILE pImage
  95
  96 /* loadaddr */
  97 #define CONFIG_LOADADDR 800000
  98
  99 /* preboot */
 100 #undef CONFIG_PREBOOT
 101
 102 /* clocks_in_mhz */
 103 #undef CONFIG_CLOCKS_IN_MHZ
 104
 105
 106 /*
 107  * High Level Configuration Options
 108  * (easy to change)
 109  */
 110
 111 #define CONFIG_MPC824X          1
 112 #define CONFIG_MPC8245          1
 113 #define CONFIG_DEBRIS           1
 114
 115 #if 0
 116 #define USE_DINK32              1
 117 #else
 118 #undef USE_DINK32
 119 #endif
 120
 121 #define CONFIG_CONS_INDEX       1
 122 #define CONFIG_BAUDRATE         9600
 123 #define CONFIG_DRAM_SPEED       100             /* MHz */
 124
 125 #define CONFIG_COMMANDS         ( CONFIG_CMD_DFL        | \
 126                                   CFG_CMD_ASKENV        | \
 127                                   CFG_CMD_CACHE         | \
 128                                   CFG_CMD_DATE          | \
 129                                   CFG_CMD_DHCP          | \
 130                                   CFG_CMD_DIAG          | \
 131                                   CFG_CMD_EEPROM        | \
 132                                   CFG_CMD_ELF           | \
 133                                   CFG_CMD_I2C           | \
 134                                   CFG_CMD_JFFS2         | \
 135                                   CFG_CMD_KGBD          | \
 136                                   CFG_CMD_PCI           | \
 137                                   CFG_CMD_PING          | \
 138                                   CFG_CMD_SAVES         | \
 139                                   CFG_CMD_SDRAM)
 140 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any)       */
 141 #include <cmd_confdefs.h>
 142
 143
 144 /*
 145  * Miscellaneous configurable options
 146  */
 147 #define CFG_LONGHELP            1               /* undef to save memory         */
 148 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt       */
 149 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 150 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size    */
 151 #define CFG_MAXARGS             16              /* max number of command args   */
 152 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 153 #define CFG_LOAD_ADDR           0x00100000      /* default load address         */
 154 #define CFG_HZ                  1000            /* decrementer freq: 1 ms ticks */
 155
 156 /*-----------------------------------------------------------------------
 157  * PCI stuff
 158  *-----------------------------------------------------------------------
 159  */
 160 #define CONFIG_PCI                              /* include pci support          */
 161 #define CONFIG_PCI_PNP
 162
 163 #define CONFIG_NET_MULTI                /* Multi ethernet cards support */
 164 #define CONFIG_EEPRO100
 165 #define CFG_RX_ETH_BUFFER       8       /* use 8 rx buffer on eepro100  */
 166 #define CONFIG_EEPRO100_SROM_WRITE
 167
 168 #define PCI_ENET0_IOADDR        0x80000000
 169 #define PCI_ENET0_MEMADDR       0x80000000
 170 #define PCI_ENET1_IOADDR        0x81000000
 171 #define PCI_ENET1_MEMADDR       0x81000000
 172 /*-----------------------------------------------------------------------
 173  * Start addresses for the final memory configuration
 174  * (Set up by the startup code)
 175  * Please note that CFG_SDRAM_BASE _must_ start at 0
 176  */
 177 #define CFG_SDRAM_BASE          0x00000000
 178 #define CFG_MAX_RAM_SIZE        0x20000000
 179 #define CONFIG_VERY_BIG_RAM
 180
 181 #define CFG_RESET_ADDRESS       0xFFF00100
 182
 183 #if defined (USE_DINK32)
 184 #define CFG_MONITOR_LEN         0x00040000
 185 #define CFG_MONITOR_BASE        0x00090000
 186 #define CFG_RAMBOOT             1
 187 #define CFG_INIT_RAM_ADDR       (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 188 #define CFG_INIT_RAM_END        0x10000
 189 #define CFG_GBL_DATA_SIZE       256  /* size in bytes reserved for initial data */
 190 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 191 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 192 #else
 193 #undef  CFG_RAMBOOT
 194 #define CFG_MONITOR_LEN         0x00040000
 195 #define CFG_MONITOR_BASE        TEXT_BASE
 196
 197 /*#define CFG_GBL_DATA_SIZE    256*/
 198 #define CFG_GBL_DATA_SIZE       128
 199
 200 #define CFG_INIT_RAM_ADDR     0x40000000
 201 #define CFG_INIT_RAM_END      0x1000
 202 #define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 203
 204 #endif
 205
 206 #define CFG_FLASH_BASE          0x7C000000
 207 #define CFG_FLASH_SIZE          (16*1024*1024)  /* debris has tiny eeprom       */
 208
 209 #define CFG_MALLOC_LEN          (512 << 10)     /* Reserve 512 kB for malloc()  */
 210
 211 #define CFG_MEMTEST_START       0x00000000      /* memtest works on             */
 212 #define CFG_MEMTEST_END         0x04000000      /* 0 ... 32 MB in DRAM          */
 213
 214 #define CFG_EUMB_ADDR           0xFC000000
 215
 216 #define CFG_FLASH_RANGE_BASE    0xFF000000      /* flash memory address range   */
 217 #define CFG_FLASH_RANGE_SIZE    0x01000000
 218 #define FLASH_BASE0_PRELIM      0x7C000000      /* debris flash         */
 219
 220 /*
 221  * JFFS2 partitions
 222  *
 223  */
 224 /* No command line, one static partition, whole device */
 225 #undef CONFIG_JFFS2_CMDLINE
 226 #define CONFIG_JFFS2_DEV                "nor0"
 227 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 228 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 229
 230 /* mtdparts command line support */
 231
 232 /* Use first bank for JFFS2, second bank contains U-Boot.
 233  *
 234  * Note: fake mtd_id's used, no linux mtd map file.
 235  */
 236 /*
 237 #define CONFIG_JFFS2_CMDLINE
 238 #define MTDIDS_DEFAULT          "nor0=debris-0"
 239 #define MTDPARTS_DEFAULT        "mtdparts=debris-0:-(jffs2)"
 240 */
 241
 242 #define CFG_ENV_IS_IN_NVRAM      1
 243 #define CONFIG_ENV_OVERWRITE     1
 244 #define CFG_NVRAM_ACCESS_ROUTINE 1
 245 #define CFG_ENV_ADDR            0xFF000000 /* right at the start of NVRAM  */
 246 #define CFG_ENV_SIZE            0x400   /* Size of the Environment - 8K    */
 247 #define CFG_ENV_OFFSET          0       /* starting right at the beginning */
 248
 249 #define CFG_NVRAM_BASE_ADDR     0xff000000
 250
 251 /*
 252  * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS =
 253  * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
 254  */
 255 #define CFG_NVRAM_VXWORKS_OFFS  0x6900
 256
 257 /*
 258  * select i2c support configuration
 259  *
 260  * Supported configurations are {none, software, hardware} drivers.
 261  * If the software driver is chosen, there are some additional
 262  * configuration items that the driver uses to drive the port pins.
 263  */
 264 #define CONFIG_HARD_I2C         1               /* To enable I2C support        */
 265 #undef  CONFIG_SOFT_I2C                         /* I2C bit-banged               */
 266 #define CFG_I2C_SPEED           400000          /* I2C speed and slave address  */
 267 #define CFG_I2C_SLAVE           0x7F
 268
 269 #ifdef CONFIG_SOFT_I2C
 270 #error "Soft I2C is not configured properly.  Please review!"
 271 #define I2C_PORT                3               /* Port A=0, B=1, C=2, D=3 */
 272 #define I2C_ACTIVE              (iop->pdir |=  0x00010000)
 273 #define I2C_TRISTATE            (iop->pdir &= ~0x00010000)
 274 #define I2C_READ                ((iop->pdat & 0x00010000) != 0)
 275 #define I2C_SDA(bit)            if(bit) iop->pdat |=  0x00010000; \
 276                                 else    iop->pdat &= ~0x00010000
 277 #define I2C_SCL(bit)            if(bit) iop->pdat |=  0x00020000; \
 278                                 else    iop->pdat &= ~0x00020000
 279 #define I2C_DELAY               udelay(5)       /* 1/4 I2C clock duration */
 280 #endif /* CONFIG_SOFT_I2C */
 281
 282 #define CFG_I2C_EEPROM_ADDR     0x57            /* EEPROM IS24C02               */
 283 #define CFG_I2C_EEPROM_ADDR_LEN 1               /* Bytes of address             */
 284 #define CFG_EEPROM_PAGE_WRITE_BITS      3
 285 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
 286
 287 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 288 #define CFG_FLASH_BANKS         { FLASH_BASE0_PRELIM }
 289
 290 /*-----------------------------------------------------------------------
 291  * Definitions for initial stack pointer and data area (in DPRAM)
 292  */
 293
 294 /*
 295  * NS16550 Configuration
 296  */
 297 #define CFG_NS16550
 298 #define CFG_NS16550_SERIAL
 299
 300 #define CFG_NS16550_REG_SIZE    1
 301
 302 #define CFG_NS16550_CLK         7372800
 303
 304 #define CFG_NS16550_COM1        0xFF080000
 305 #define CFG_NS16550_COM2        (CFG_NS16550_COM1 + 8)
 306 #define CFG_NS16550_COM3        (CFG_NS16550_COM1 + 16)
 307 #define CFG_NS16550_COM4        (CFG_NS16550_COM1 + 24)
 308
 309 /*
 310  * Low Level Configuration Settings
 311  * (address mappings, register initial values, etc.)
 312  * You should know what you are doing if you make changes here.
 313  */
 314
 315 #define CONFIG_SYS_CLK_FREQ  33333333   /* external frequency to pll */
 316 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
 317
 318 #define CFG_DLL_EXTEND          0x00
 319 #define CFG_PCI_HOLD_DEL        0x20
 320
 321 #define CFG_ROMNAL      15      /* rom/flash next access time */
 322 #define CFG_ROMFAL      31      /* rom/flash access time */
 323
 324 #define CFG_REFINT      430     /* # of clocks between CBR refresh cycles */
 325
 326 #define CFG_DBUS_SIZE2  1       /* set for 8-bit RCS1, clear for 32,64 */
 327
 328 /* the following are for SDRAM only*/
 329 #define CFG_BSTOPRE     121     /* Burst To Precharge, sets open page interval */
 330 #define CFG_REFREC      8       /* Refresh to activate interval         */
 331 #define CFG_RDLAT       4       /* data latency from read command       */
 332 #define CFG_PRETOACT    3       /* Precharge to activate interval       */
 333 #define CFG_ACTTOPRE    5       /* Activate to Precharge interval       */
 334 #define CFG_ACTORW              3       /* Activate to R/W                      */
 335 #define CFG_SDMODE_CAS_LAT      3       /* SDMODE CAS latency                   */
 336 #define CFG_SDMODE_WRAP         0       /* SDMODE wrap type                     */
 337 #if 0
 338 #define CFG_SDMODE_BURSTLEN     2       /* OBSOLETE!  SDMODE Burst length 2=4, 3=8              */
 339 #endif
 340
 341 #define CFG_REGISTERD_TYPE_BUFFER   1
 342 #define CFG_EXTROM 1
 343 #define CFG_REGDIMM 0
 344
 345
 346 /* memory bank settings*/
 347 /*
 348  * only bits 20-29 are actually used from these vales to set the
 349  * start/end address the upper two bits will be 0, and the lower 20
 350  * bits will be set to 0x00000 for a start address, or 0xfffff for an
 351  * end address
 352  */
 353 #define CFG_BANK0_START         0x00000000
 354 #define CFG_BANK0_END           (0x4000000 - 1)
 355 #define CFG_BANK0_ENABLE        1
 356 #define CFG_BANK1_START         0x04000000
 357 #define CFG_BANK1_END           (0x8000000 - 1)
 358 #define CFG_BANK1_ENABLE        1
 359 #define CFG_BANK2_START         0x3ff00000
 360 #define CFG_BANK2_END           0x3fffffff
 361 #define CFG_BANK2_ENABLE        0
 362 #define CFG_BANK3_START         0x3ff00000
 363 #define CFG_BANK3_END           0x3fffffff
 364 #define CFG_BANK3_ENABLE        0
 365 #define CFG_BANK4_START         0x00000000
 366 #define CFG_BANK4_END           0x00000000
 367 #define CFG_BANK4_ENABLE        0
 368 #define CFG_BANK5_START         0x00000000
 369 #define CFG_BANK5_END           0x00000000
 370 #define CFG_BANK5_ENABLE        0
 371 #define CFG_BANK6_START         0x00000000
 372 #define CFG_BANK6_END           0x00000000
 373 #define CFG_BANK6_ENABLE        0
 374 #define CFG_BANK7_START         0x00000000
 375 #define CFG_BANK7_END           0x00000000
 376 #define CFG_BANK7_ENABLE        0
 377 /*
 378  * Memory bank enable bitmask, specifying which of the banks defined above
 379  are actually present. MSB is for bank #7, LSB is for bank #0.
 380  */
 381 #define CFG_BANK_ENABLE         0x01
 382
 383 #define CFG_ODCR                0x75    /* configures line driver impedances,   */
 384                                         /* see 8240 book for bit definitions    */
 385 #define CFG_PGMAX               0x32    /* how long the 8240 retains the        */
 386                                         /* currently accessed page in memory    */
 387                                         /* see 8240 book for details            */
 388
 389 /* SDRAM 0 - 256MB */
 390 #define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 391 #define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 392
 393 /* stack in DCACHE @ 1GB (no backing mem) */
 394 #if defined(USE_DINK32)
 395 #define CFG_IBAT1L      (0x40000000 | BATL_PP_00 )
 396 #define CFG_IBAT1U      (0x40000000 | BATU_BL_128K )
 397 #else
 398 #define CFG_IBAT1L      (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 399 #define CFG_IBAT1U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 400 #endif
 401
 402 /* PCI memory */
 403 #define CFG_IBAT2L      (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 404 #define CFG_IBAT2U      (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 405
 406 /* Flash, config addrs, etc */
 407 #define CFG_IBAT3L      (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 408 #define CFG_IBAT3U      (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 409
 410 #define CFG_DBAT0L      CFG_IBAT0L
 411 #define CFG_DBAT0U      CFG_IBAT0U
 412 #define CFG_DBAT1L      CFG_IBAT1L
 413 #define CFG_DBAT1U      CFG_IBAT1U
 414 #define CFG_DBAT2L      CFG_IBAT2L
 415 #define CFG_DBAT2U      CFG_IBAT2U
 416 #define CFG_DBAT3L      CFG_IBAT3L
 417 #define CFG_DBAT3U      CFG_IBAT3U
 418
 419 /*
 420  * For booting Linux, the board info and command line data
 421  * have to be in the first 8 MB of memory, since this is
 422  * the maximum mapped by the Linux kernel during initialization.
 423  */
 424 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 425 /*-----------------------------------------------------------------------
 426  * FLASH organization
 427  */
 428 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 429 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 430
 431 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 432 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 433
 434 /*-----------------------------------------------------------------------
 435  * Cache Configuration
 436  */
 437 #define CFG_CACHELINE_SIZE      32      /* For MPC8240 CPU                      */
 438 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 439 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 440 #endif
 441
 442
 443 /*
 444  * Internal Definitions
 445  *
 446  * Boot Flags
 447  */
 448 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH     */
 449 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
 450
 451
 452 /* values according to the manual */
 453
 454 #define CONFIG_DRAM_50MHZ       1
 455 #define CONFIG_SDRAM_50MHZ
 456
 457 #define CONFIG_DISK_SPINUP_TIME 1000000
 458
 459 #endif  /* __CONFIG_H */