include/configs/devkit3250.h

   1 /*
   2  * Embest/Timll DevKit3250 board configuration file
   3  *
   4  * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_DEVKIT3250_H__
  10 #define __CONFIG_DEVKIT3250_H__
  11
  12 /* SoC and board defines */
  13 #include <linux/sizes.h>
  14 #include <asm/arch/cpu.h>
  15
  16 /*
  17  * Define DevKit3250 machine type by hand until it lands in mach-types
  18  */
  19 #define MACH_TYPE_DEVKIT3250            3697
  20 #define CONFIG_MACH_TYPE                MACH_TYPE_DEVKIT3250
  21
  22 #define CONFIG_SYS_ICACHE_OFF
  23 #define CONFIG_SYS_DCACHE_OFF
  24 #if !defined(CONFIG_SPL_BUILD)
  25 #define CONFIG_SKIP_LOWLEVEL_INIT
  26 #endif
  27 #define CONFIG_BOARD_EARLY_INIT_F
  28
  29 /*
  30  * Memory configurations
  31  */
  32 #define CONFIG_NR_DRAM_BANKS            1
  33 #define CONFIG_SYS_MALLOC_LEN           SZ_1M
  34 #define CONFIG_SYS_SDRAM_BASE           EMC_DYCS0_BASE
  35 #define CONFIG_SYS_SDRAM_SIZE           SZ_64M
  36 #define CONFIG_SYS_TEXT_BASE            0x83F00000
  37 #define CONFIG_SYS_MEMTEST_START        (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  38 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_TEXT_BASE - SZ_1M)
  39
  40 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  41
  42 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + SZ_4K \
  43                                          - GENERATED_GBL_DATA_SIZE)
  44
  45 /*
  46  * Serial Driver
  47  */
  48 #define CONFIG_SYS_LPC32XX_UART         5   /* UART5 */
  49 #define CONFIG_BAUDRATE                 115200
  50
  51 /*
  52  * DMA
  53  */
  54 #if !defined(CONFIG_SPL_BUILD)
  55 #define CONFIG_DMA_LPC32XX
  56 #endif
  57
  58 /*
  59  * I2C
  60  */
  61 #define CONFIG_SYS_I2C
  62 #define CONFIG_SYS_I2C_LPC32XX
  63 #define CONFIG_SYS_I2C_SPEED            100000
  64 #define CONFIG_CMD_I2C
  65
  66 /*
  67  * GPIO
  68  */
  69 #define CONFIG_LPC32XX_GPIO
  70
  71 /*
  72  * SSP/SPI
  73  */
  74 #define CONFIG_LPC32XX_SSP
  75 #define CONFIG_LPC32XX_SSP_TIMEOUT      100000
  76 #define CONFIG_CMD_SPI
  77
  78 /*
  79  * Ethernet
  80  */
  81 #define CONFIG_RMII
  82 #define CONFIG_PHY_SMSC
  83 #define CONFIG_LPC32XX_ETH
  84 #define CONFIG_PHYLIB
  85 #define CONFIG_PHY_ADDR                 0x1F
  86 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  87 #define CONFIG_CMD_MII
  88 #define CONFIG_CMD_PING
  89 #define CONFIG_CMD_DHCP
  90
  91 /*
  92  * NOR Flash
  93  */
  94 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  95 #define CONFIG_SYS_MAX_FLASH_SECT       71
  96 #define CONFIG_SYS_FLASH_BASE           EMC_CS0_BASE
  97 #define CONFIG_SYS_FLASH_SIZE           SZ_4M
  98 #define CONFIG_SYS_FLASH_CFI
  99
 100 /*
 101  * NAND controller
 102  */
 103 #define CONFIG_NAND_LPC32XX_SLC
 104 #define CONFIG_SYS_NAND_BASE            SLC_NAND_BASE
 105 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 106 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 107
 108 /*
 109  * NAND chip timings
 110  */
 111 #define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS        14
 112 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH          66666666
 113 #define CONFIG_LPC32XX_NAND_SLC_WHOLD           200000000
 114 #define CONFIG_LPC32XX_NAND_SLC_WSETUP          50000000
 115 #define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS        14
 116 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH          66666666
 117 #define CONFIG_LPC32XX_NAND_SLC_RHOLD           200000000
 118 #define CONFIG_LPC32XX_NAND_SLC_RSETUP          50000000
 119
 120 #define CONFIG_SYS_NAND_BLOCK_SIZE              0x20000
 121 #define CONFIG_SYS_NAND_PAGE_SIZE               NAND_LARGE_BLOCK_PAGE_SIZE
 122 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 123
 124 #define CONFIG_CMD_JFFS2
 125 #define CONFIG_CMD_NAND
 126
 127 /*
 128  * USB
 129  */
 130 #define CONFIG_USB_OHCI_LPC32XX
 131 #define CONFIG_USB_ISP1301_I2C_ADDR             0x2d
 132 #define CONFIG_USB_STORAGE
 133 #define CONFIG_CMD_FAT
 134 #define CONFIG_CMD_USB
 135
 136 /*
 137  * U-Boot General Configurations
 138  */
 139 #define CONFIG_SYS_LONGHELP
 140 #define CONFIG_SYS_CBSIZE               1024
 141 #define CONFIG_SYS_PBSIZE               \
 142         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 143 #define CONFIG_SYS_MAXARGS              16
 144 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 145
 146 #define CONFIG_AUTO_COMPLETE
 147 #define CONFIG_CMDLINE_EDITING
 148 #define CONFIG_VERSION_VARIABLE
 149 #define CONFIG_DISPLAY_CPUINFO
 150 #define CONFIG_DOS_PARTITION
 151
 152 /*
 153  * Pass open firmware flat tree
 154  */
 155
 156 /*
 157  * Environment
 158  */
 159 #define CONFIG_ENV_IS_IN_NAND           1
 160 #define CONFIG_ENV_SIZE                 SZ_128K
 161 #define CONFIG_ENV_OFFSET               0x000A0000
 162
 163 #define CONFIG_BOOTCOMMAND                      \
 164         "dhcp; "                                \
 165         "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; "         \
 166         "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; "       \
 167         "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; "     \
 168         "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; "                  \
 169         "bootm ${loadaddr} - ${dtbaddr}"
 170
 171 #define CONFIG_EXTRA_ENV_SETTINGS               \
 172         "autoload=no\0"                         \
 173         "ethaddr=00:01:90:00:C0:81\0"           \
 174         "dtbaddr=0x81000000\0"                  \
 175         "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0"  \
 176         "tftpdir=vladimir/oe/devkit3250\0"      \
 177         "userargs=oops=panic\0"
 178
 179 /*
 180  * U-Boot Commands
 181  */
 182 #define CONFIG_CMD_CACHE
 183
 184 /*
 185  * Boot Linux
 186  */
 187 #define CONFIG_CMDLINE_TAG
 188 #define CONFIG_SETUP_MEMORY_TAGS
 189 #define CONFIG_ZERO_BOOTDELAY_CHECK
 190 #define CONFIG_BOOTDELAY                1
 191
 192 #define CONFIG_BOOTFILE                 "uImage"
 193 #define CONFIG_BOOTARGS                 "console=ttyS0,115200n8"
 194 #define CONFIG_LOADADDR                 0x80008000
 195
 196 /*
 197  * SPL specific defines
 198  */
 199 /* SPL will be executed at offset 0 */
 200 #define CONFIG_SPL_TEXT_BASE            0x00000000
 201
 202 /* SPL will use SRAM as stack */
 203 #define CONFIG_SPL_STACK                0x0000FFF8
 204 #define CONFIG_SPL_BOARD_INIT
 205
 206 /* Use the framework and generic lib */
 207 #define CONFIG_SPL_FRAMEWORK
 208 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 209 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 210
 211 /* SPL will use serial */
 212 #define CONFIG_SPL_SERIAL_SUPPORT
 213
 214 /* SPL loads an image from NAND */
 215 #define CONFIG_SPL_NAND_SIMPLE
 216 #define CONFIG_SPL_NAND_RAW_ONLY
 217 #define CONFIG_SPL_NAND_SUPPORT
 218 #define CONFIG_SPL_NAND_DRIVERS
 219
 220 #define CONFIG_SPL_NAND_ECC
 221 #define CONFIG_SPL_NAND_SOFTECC
 222
 223 #define CONFIG_SPL_MAX_SIZE             0x20000
 224 #define CONFIG_SPL_PAD_TO               CONFIG_SPL_MAX_SIZE
 225
 226 /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
 227 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 228 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x60000
 229
 230 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 231 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 232
 233 /* See common/spl/spl.c  spl_set_header_raw_uboot() */
 234 #define CONFIG_SYS_MONITOR_LEN          CONFIG_SYS_NAND_U_BOOT_SIZE
 235
 236 /*
 237  * Include SoC specific configuration
 238  */
 239 #include <asm/arch/config.h>
 240
 241 #endif  /* __CONFIG_DEVKIT3250_H__*/