include/configs/devkit3250.h

   1 /*
   2  * Embest/Timll DevKit3250 board configuration file
   3  *
   4  * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_DEVKIT3250_H__
  10 #define __CONFIG_DEVKIT3250_H__
  11
  12 /* SoC and board defines */
  13 #include <linux/sizes.h>
  14 #include <asm/arch/cpu.h>
  15
  16 #define CONFIG_MACH_TYPE                MACH_TYPE_DEVKIT3250
  17
  18 #define CONFIG_SYS_ICACHE_OFF
  19 #define CONFIG_SYS_DCACHE_OFF
  20 #if !defined(CONFIG_SPL_BUILD)
  21 #define CONFIG_SKIP_LOWLEVEL_INIT
  22 #endif
  23
  24 /*
  25  * Memory configurations
  26  */
  27 #define CONFIG_NR_DRAM_BANKS            1
  28 #define CONFIG_SYS_MALLOC_LEN           SZ_1M
  29 #define CONFIG_SYS_SDRAM_BASE           EMC_DYCS0_BASE
  30 #define CONFIG_SYS_SDRAM_SIZE           SZ_64M
  31 #define CONFIG_SYS_MEMTEST_START        (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  32 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_TEXT_BASE - SZ_1M)
  33
  34 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  35
  36 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + SZ_4K \
  37                                          - GENERATED_GBL_DATA_SIZE)
  38
  39 /*
  40  * Serial Driver
  41  */
  42 #define CONFIG_SYS_LPC32XX_UART         5   /* UART5 */
  43
  44 /*
  45  * DMA
  46  */
  47 #if !defined(CONFIG_SPL_BUILD)
  48 #define CONFIG_DMA_LPC32XX
  49 #endif
  50
  51 /*
  52  * I2C
  53  */
  54 #define CONFIG_SYS_I2C
  55 #define CONFIG_SYS_I2C_LPC32XX
  56 #define CONFIG_SYS_I2C_SPEED            100000
  57
  58 /*
  59  * GPIO
  60  */
  61 #define CONFIG_LPC32XX_GPIO
  62
  63 /*
  64  * SSP/SPI
  65  */
  66 #define CONFIG_LPC32XX_SSP
  67 #define CONFIG_LPC32XX_SSP_TIMEOUT      100000
  68
  69 /*
  70  * Ethernet
  71  */
  72 #define CONFIG_RMII
  73 #define CONFIG_PHY_SMSC
  74 #define CONFIG_LPC32XX_ETH
  75 #define CONFIG_PHY_ADDR                 0x1F
  76 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  77
  78 /*
  79  * NOR Flash
  80  */
  81 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  82 #define CONFIG_SYS_MAX_FLASH_SECT       71
  83 #define CONFIG_SYS_FLASH_BASE           EMC_CS0_BASE
  84 #define CONFIG_SYS_FLASH_SIZE           SZ_4M
  85 #define CONFIG_SYS_FLASH_CFI
  86
  87 /*
  88  * NAND controller
  89  */
  90 #define CONFIG_NAND_LPC32XX_SLC
  91 #define CONFIG_SYS_NAND_BASE            SLC_NAND_BASE
  92 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  93 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
  94
  95 /*
  96  * NAND chip timings
  97  */
  98 #define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS        14
  99 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH          66666666
 100 #define CONFIG_LPC32XX_NAND_SLC_WHOLD           200000000
 101 #define CONFIG_LPC32XX_NAND_SLC_WSETUP          50000000
 102 #define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS        14
 103 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH          66666666
 104 #define CONFIG_LPC32XX_NAND_SLC_RHOLD           200000000
 105 #define CONFIG_LPC32XX_NAND_SLC_RSETUP          50000000
 106
 107 #define CONFIG_SYS_NAND_BLOCK_SIZE              0x20000
 108 #define CONFIG_SYS_NAND_PAGE_SIZE               NAND_LARGE_BLOCK_PAGE_SIZE
 109 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 110
 111 /*
 112  * USB
 113  */
 114 #define CONFIG_USB_OHCI_LPC32XX
 115 #define CONFIG_USB_ISP1301_I2C_ADDR             0x2d
 116
 117 /*
 118  * U-Boot General Configurations
 119  */
 120 #define CONFIG_SYS_LONGHELP
 121 #define CONFIG_SYS_CBSIZE               1024
 122 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 123
 124 #define CONFIG_AUTO_COMPLETE
 125 #define CONFIG_CMDLINE_EDITING
 126
 127 /*
 128  * Pass open firmware flat tree
 129  */
 130
 131 /*
 132  * Environment
 133  */
 134 #define CONFIG_ENV_SIZE                 SZ_128K
 135 #define CONFIG_ENV_OFFSET               0x000A0000
 136
 137 #define CONFIG_BOOTCOMMAND                      \
 138         "dhcp; "                                \
 139         "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; "         \
 140         "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; "       \
 141         "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; "     \
 142         "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; "                  \
 143         "bootm ${loadaddr} - ${dtbaddr}"
 144
 145 #define CONFIG_EXTRA_ENV_SETTINGS               \
 146         "autoload=no\0"                         \
 147         "ethaddr=00:01:90:00:C0:81\0"           \
 148         "dtbaddr=0x81000000\0"                  \
 149         "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0"  \
 150         "tftpdir=vladimir/oe/devkit3250\0"      \
 151         "userargs=oops=panic\0"
 152
 153 /*
 154  * U-Boot Commands
 155  */
 156
 157 /*
 158  * Boot Linux
 159  */
 160 #define CONFIG_CMDLINE_TAG
 161 #define CONFIG_SETUP_MEMORY_TAGS
 162
 163 #define CONFIG_BOOTFILE                 "uImage"
 164 #define CONFIG_LOADADDR                 0x80008000
 165
 166 /*
 167  * SPL specific defines
 168  */
 169 /* SPL will be executed at offset 0 */
 170 #define CONFIG_SPL_TEXT_BASE            0x00000000
 171
 172 /* SPL will use SRAM as stack */
 173 #define CONFIG_SPL_STACK                0x0000FFF8
 174
 175 /* Use the framework and generic lib */
 176 #define CONFIG_SPL_FRAMEWORK
 177
 178 /* SPL will use serial */
 179
 180 /* SPL loads an image from NAND */
 181 #define CONFIG_SPL_NAND_RAW_ONLY
 182 #define CONFIG_SPL_NAND_DRIVERS
 183
 184 #define CONFIG_SPL_NAND_ECC
 185 #define CONFIG_SPL_NAND_SOFTECC
 186
 187 #define CONFIG_SPL_MAX_SIZE             0x20000
 188 #define CONFIG_SPL_PAD_TO               CONFIG_SPL_MAX_SIZE
 189
 190 /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
 191 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 192 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x60000
 193
 194 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 195 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 196
 197 /* See common/spl/spl.c  spl_set_header_raw_uboot() */
 198 #define CONFIG_SYS_MONITOR_LEN          CONFIG_SYS_NAND_U_BOOT_SIZE
 199
 200 /*
 201  * Include SoC specific configuration
 202  */
 203 #include <asm/arch/config.h>
 204
 205 #endif  /* __CONFIG_DEVKIT3250_H__*/