include/configs/dlvision-10g.h

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #define CONFIG_405EP            1       /* this is a PPC405 CPU */
  12 #define CONFIG_DLVISION_10G     1       /*  on a DLVision-10G board */
  13
  14 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  15
  16 /*
  17  * Include common defines/options for all AMCC eval boards
  18  */
  19 #define CONFIG_HOSTNAME         dlvsion-10g
  20 #define CONFIG_IDENT_STRING     " dlvision-10g 0.06"
  21 #include "amcc-common.h"
  22
  23 #define CONFIG_BOARD_EARLY_INIT_F
  24 #define CONFIG_BOARD_EARLY_INIT_R
  25 #define CONFIG_MISC_INIT_R
  26 #define CONFIG_LAST_STAGE_INIT
  27
  28 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  29
  30 #undef CONFIG_ZERO_BOOTDELAY_CHECK     /* ignore keypress on bootdelay==0 */
  31
  32 /*
  33  * Configure PLL
  34  */
  35 #define PLLMR0_DEFAULT PLLMR0_266_133_66
  36 #define PLLMR1_DEFAULT PLLMR1_266_133_66
  37
  38 /* new uImage format support */
  39 #define CONFIG_FIT_DISABLE_SHA256
  40
  41 #define CONFIG_ENV_IS_IN_FLASH  /* use FLASH for environment vars */
  42
  43 /*
  44  * Default environment variables
  45  */
  46 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  47         CONFIG_AMCC_DEF_ENV                                             \
  48         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
  49         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
  50         "kernel_addr=fc000000\0"                                        \
  51         "fdt_addr=fc1e0000\0"                                           \
  52         "ramdisk_addr=fc200000\0"                                       \
  53         ""
  54
  55 #define CONFIG_PHY_ADDR         4       /* PHY address                  */
  56 #define CONFIG_HAS_ETH0
  57 #define CONFIG_HAS_ETH1
  58 #define CONFIG_PHY1_ADDR        0xc     /* EMAC1 PHY address            */
  59 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ
  60
  61 /*
  62  * Commands additional to the ones defined in amcc-common.h
  63  */
  64 #define CONFIG_CMD_DTT
  65 #undef CONFIG_CMD_DHCP
  66 #undef CONFIG_CMD_DIAG
  67 #undef CONFIG_CMD_EEPROM
  68 #define CONFIG_CMD_I2C
  69 #undef CONFIG_CMD_IRQ
  70
  71 /*
  72  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  73  */
  74 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  75
  76 /* SDRAM timings used in datasheet */
  77 #define CONFIG_SYS_SDRAM_CL             3       /* CAS latency */
  78 #define CONFIG_SYS_SDRAM_tRP           20       /* PRECHARGE command period */
  79 #define CONFIG_SYS_SDRAM_tRC           66       /* ACTIVE-to-ACTIVE period */
  80 #define CONFIG_SYS_SDRAM_tRCD          20       /* ACTIVE-to-READ delay */
  81 #define CONFIG_SYS_SDRAM_tRFC          66       /* Auto refresh period */
  82
  83 /*
  84  * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  85  * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
  86  * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
  87  * The Linux BASE_BAUD define should match this configuration.
  88  *    baseBaud = cpuClock/(uartDivisor*16)
  89  * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  90  * set Linux BASE_BAUD to 403200.
  91  */
  92 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  93 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK     /* external serial clock */
  94 #undef  CONFIG_SYS_405_UART_ERRATA_59   /* 405GP/CR Rev. D silicon */
  95 #define CONFIG_SYS_BASE_BAUD            691200
  96
  97 /*
  98  * I2C stuff
  99  */
 100 #define CONFIG_SYS_I2C_PPC4XX
 101 #define CONFIG_SYS_I2C_PPC4XX_CH0
 102 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
 103 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 104
 105 #define CONFIG_SYS_I2C_IHS
 106 #define CONFIG_SYS_I2C_IHS_DUAL
 107 #define CONFIG_SYS_I2C_IHS_CH0
 108 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 109 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 110 #define CONFIG_SYS_I2C_IHS_SPEED_0_1            50000
 111 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1            0x7F
 112 #define CONFIG_SYS_I2C_IHS_CH1
 113 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 114 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 115 #define CONFIG_SYS_I2C_IHS_SPEED_1_1            50000
 116 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1            0x7F
 117
 118 #define CONFIG_SYS_SPD_BUS_NUM          4
 119
 120 /* Temp sensor/hwmon/dtt */
 121 #define CONFIG_SYS_DTT_BUS_NUM  4
 122 #define CONFIG_DTT_LM63         1       /* National LM63        */
 123 #define CONFIG_DTT_SENSORS      { 0x4c, 0x4e, 0x18 } /* Sensor addresses */
 124 #define CONFIG_DTT_PWM_LOOKUPTABLE      \
 125                 { { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
 126                   { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
 127 #define CONFIG_DTT_TACH_LIMIT   0xa10
 128
 129 #define CONFIG_SYS_ICS8N3QV01_I2C       {1, 3}
 130 #define CONFIG_SYS_SIL1178_I2C          {0, 2}
 131 #define CONFIG_SYS_DP501_I2C            {0, 2}
 132
 133 /* EBC peripherals */
 134
 135 #define CONFIG_SYS_FLASH_BASE           0xFC000000
 136 #define CONFIG_SYS_FPGA0_BASE           0x7f100000
 137 #define CONFIG_SYS_FPGA1_BASE           0x7f200000
 138 #define CONFIG_SYS_LATCH_BASE           0x7f300000
 139
 140 #define CONFIG_SYS_FPGA_BASE(k) \
 141         (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
 142
 143 #define CONFIG_SYS_FPGA_DONE(k) \
 144         (k ? 0x2000 : 0x1000)
 145
 146 #define CONFIG_SYS_FPGA_COUNT           2
 147
 148 #define CONFIG_SYS_FPGA_PTR { \
 149         (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
 150         (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
 151
 152 #define CONFIG_SYS_FPGA_COMMON
 153
 154 #define CONFIG_SYS_LATCH0_RESET         0xffff
 155 #define CONFIG_SYS_LATCH0_BOOT          0xffff
 156 #define CONFIG_SYS_LATCH1_RESET         0xffbf
 157 #define CONFIG_SYS_LATCH1_BOOT          0xffff
 158
 159 #define CONFIG_SYS_FPGA_NO_RFL_HI
 160
 161 /*
 162  * FLASH organization
 163  */
 164 #define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 165 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 166
 167 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 168
 169 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 170 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sectors per chip*/
 171
 172 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase/ms */
 173 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write/ms */
 174
 175 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buff'd writes */
 176
 177 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* 'E' for empty sector on flinfo */
 178 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* no warn upon unknown flash */
 179
 180 #ifdef CONFIG_ENV_IS_IN_FLASH
 181 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector */
 182 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 183 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector */
 184
 185 /* Address and size of Redundant Environment Sector     */
 186 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 187 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 188 #endif
 189
 190 /*
 191  * PPC405 GPIO Configuration
 192  */
 193 #define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO     Alternate1      */ \
 194 { \
 195 /* GPIO Core 0 */ \
 196 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast */ \
 197 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E */ \
 198 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E */ \
 199 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O */ \
 200 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O */ \
 201 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5   TS3 */ \
 202 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6   TS4 */ \
 203 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO7   TS5 */ \
 204 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6 */ \
 205 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9   TrcClk */ \
 206 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1 */ \
 207 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2 */ \
 208 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3 */ \
 209 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4 */ \
 210 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03 */ \
 211 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04 */ \
 212 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05 */ \
 213 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0 */ \
 214 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1 */ \
 215 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2 */ \
 216 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3 */ \
 217 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4 */ \
 218 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5 */ \
 219 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6 */ \
 220 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD */ \
 221 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR */ \
 222 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI */ \
 223 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR */ \
 224 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx */ \
 225 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx */ \
 226 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
 227 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
 228 } \
 229 }
 230
 231 /*
 232  * Definitions for initial stack pointer and data area (in data cache)
 233  */
 234 /* use on chip memory (OCM) for temperary stack until sdram is tested */
 235 #define CONFIG_SYS_TEMP_STACK_OCM       1
 236
 237 /* On Chip Memory location */
 238 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 239 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 240 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
 241 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE
 242
 243 #define CONFIG_SYS_GBL_DATA_OFFSET \
 244         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 245 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 246
 247 /*
 248  * External Bus Controller (EBC) Setup
 249  */
 250
 251 /* Memory Bank 0 (NOR-flash) */
 252 #define CONFIG_SYS_EBC_PB0AP    (EBC_BXAP_BME_ENABLED           |       \
 253                                  EBC_BXAP_FWT_ENCODE(8)         |       \
 254                                  EBC_BXAP_BWT_ENCODE(7)         |       \
 255                                  EBC_BXAP_BCE_DISABLE           |       \
 256                                  EBC_BXAP_BCT_2TRANS            |       \
 257                                  EBC_BXAP_CSN_ENCODE(0)         |       \
 258                                  EBC_BXAP_OEN_ENCODE(2)         |       \
 259                                  EBC_BXAP_WBN_ENCODE(2)         |       \
 260                                  EBC_BXAP_WBF_ENCODE(2)         |       \
 261                                  EBC_BXAP_TH_ENCODE(4)          |       \
 262                                  EBC_BXAP_RE_DISABLED           |       \
 263                                  EBC_BXAP_SOR_NONDELAYED        |       \
 264                                  EBC_BXAP_BEM_WRITEONLY         |       \
 265                                  EBC_BXAP_PEN_DISABLED)
 266 #define CONFIG_SYS_EBC_PB0CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
 267                                  EBC_BXCR_BS_64MB               |       \
 268                                  EBC_BXCR_BU_RW                 |       \
 269                                  EBC_BXCR_BW_16BIT)
 270
 271 /* Memory Bank 1 (FPGA0) */
 272 #define CONFIG_SYS_EBC_PB1AP    (EBC_BXAP_BME_DISABLED          |       \
 273                                  EBC_BXAP_TWT_ENCODE(5)         |       \
 274                                  EBC_BXAP_BCE_DISABLE           |       \
 275                                  EBC_BXAP_BCT_2TRANS            |       \
 276                                  EBC_BXAP_CSN_ENCODE(0)         |       \
 277                                  EBC_BXAP_OEN_ENCODE(2)         |       \
 278                                  EBC_BXAP_WBN_ENCODE(1)         |       \
 279                                  EBC_BXAP_WBF_ENCODE(1)         |       \
 280                                  EBC_BXAP_TH_ENCODE(0)          |       \
 281                                  EBC_BXAP_RE_DISABLED           |       \
 282                                  EBC_BXAP_SOR_NONDELAYED        |       \
 283                                  EBC_BXAP_BEM_WRITEONLY         |       \
 284                                  EBC_BXAP_PEN_DISABLED)
 285 #define CONFIG_SYS_EBC_PB1CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
 286                                  EBC_BXCR_BS_1MB                |       \
 287                                  EBC_BXCR_BU_RW                 |       \
 288                                  EBC_BXCR_BW_16BIT)
 289
 290 /* Memory Bank 2 (FPGA1) */
 291 #define CONFIG_SYS_EBC_PB2AP    (EBC_BXAP_BME_DISABLED          |       \
 292                                  EBC_BXAP_TWT_ENCODE(6)         |       \
 293                                  EBC_BXAP_BCE_DISABLE           |       \
 294                                  EBC_BXAP_BCT_2TRANS            |       \
 295                                  EBC_BXAP_CSN_ENCODE(0)         |       \
 296                                  EBC_BXAP_OEN_ENCODE(2)         |       \
 297                                  EBC_BXAP_WBN_ENCODE(1)         |       \
 298                                  EBC_BXAP_WBF_ENCODE(1)         |       \
 299                                  EBC_BXAP_TH_ENCODE(0)          |       \
 300                                  EBC_BXAP_RE_DISABLED           |       \
 301                                  EBC_BXAP_SOR_NONDELAYED        |       \
 302                                  EBC_BXAP_BEM_WRITEONLY         |       \
 303                                  EBC_BXAP_PEN_DISABLED)
 304 #define CONFIG_SYS_EBC_PB2CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
 305                                  EBC_BXCR_BS_1MB                |       \
 306                                  EBC_BXCR_BU_RW                 |       \
 307                                  EBC_BXCR_BW_16BIT)
 308
 309 /* Memory Bank 3 (Latches) */
 310 #define CONFIG_SYS_EBC_PB3AP    (EBC_BXAP_BME_ENABLED           |       \
 311                                  EBC_BXAP_FWT_ENCODE(8)         |       \
 312                                  EBC_BXAP_BWT_ENCODE(4)         |       \
 313                                  EBC_BXAP_BCE_DISABLE           |       \
 314                                  EBC_BXAP_BCT_2TRANS            |       \
 315                                  EBC_BXAP_CSN_ENCODE(0)         |       \
 316                                  EBC_BXAP_OEN_ENCODE(1)         |       \
 317                                  EBC_BXAP_WBN_ENCODE(1)         |       \
 318                                  EBC_BXAP_WBF_ENCODE(1)         |       \
 319                                  EBC_BXAP_TH_ENCODE(2)          |       \
 320                                  EBC_BXAP_RE_DISABLED           |       \
 321                                  EBC_BXAP_SOR_NONDELAYED        |       \
 322                                  EBC_BXAP_BEM_WRITEONLY         |       \
 323                                  EBC_BXAP_PEN_DISABLED)
 324 #define CONFIG_SYS_EBC_PB3CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
 325                                  EBC_BXCR_BS_1MB                |       \
 326                                  EBC_BXCR_BU_RW                 |       \
 327                                  EBC_BXCR_BW_16BIT)
 328
 329 /*
 330  * OSD Setup
 331  */
 332 #define CONFIG_SYS_MPC92469AC
 333 #define CONFIG_SYS_OSD_SCREENS          CONFIG_SYS_FPGA_COUNT
 334 #define CONFIG_SYS_DP501_DIFFERENTIAL
 335 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 336
 337 #endif  /* __CONFIG_H */