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1 /*
2 * (C) Copyright 2013
3 * Texas Instruments Incorporated.
4 * Lokesh Vutla <lokeshvutla@ti.com>
5 *
6 * Configuration settings for the TI DRA7XX board.
7 * See ti_omap5_common.h for omap5 common settings.
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12 #ifndef __CONFIG_DRA7XX_EVM_H
13 #define __CONFIG_DRA7XX_EVM_H
14
15 #include <environment/ti/dfu.h>
16
17 #ifdef CONFIG_SPL_BUILD
18 #define CONFIG_IODELAY_RECALIBRATION
19 #endif
20
21 #define CONFIG_VERY_BIG_RAM
22 #define CONFIG_NR_DRAM_BANKS 2
23 #define CONFIG_MAX_MEM_MAPPED 0x80000000
24
25 #ifndef CONFIG_QSPI_BOOT
26 /* MMC ENV related defines */
27 #define CONFIG_ENV_IS_IN_MMC
28 #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
29 #define CONFIG_ENV_SIZE (128 << 10)
30 #define CONFIG_ENV_OFFSET 0x260000
31 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
32 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
33 #endif
34
35 #if (CONFIG_CONS_INDEX == 1)
36 #define CONSOLEDEV "ttyO0"
37 #elif (CONFIG_CONS_INDEX == 3)
38 #define CONSOLEDEV "ttyO2"
39 #endif
40 #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
41 #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
42 #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
43
44 #define CONFIG_ENV_EEPROM_IS_ON_I2C
45 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
46 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
47
48 #define CONFIG_SYS_OMAP_ABE_SYSCK
49
50 #ifndef CONFIG_SPL_BUILD
51 /* Define the default GPT table for eMMC */
52 #define PARTS_DEFAULT \
53 /* Linux partitions */ \
54 "uuid_disk=${uuid_gpt_disk};" \
55 "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
56 /* Android partitions */ \
57 "partitions_android=" \
58 "uuid_disk=${uuid_gpt_disk};" \
59 "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \
60 "name=bootloader,size=768K,uuid=${uuid_gpt_bootloader};" \
61 "name=environment,size=128K,uuid=${uuid_gpt_environment};" \
62 "name=misc,size=128K,uuid=${uuid_gpt_misc};" \
63 "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \
64 "name=efs,size=16M,uuid=${uuid_gpt_efs};" \
65 "name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \
66 "name=recovery,size=10M,uuid=${uuid_gpt_recovery};" \
67 "name=boot,size=10M,uuid=${uuid_gpt_boot};" \
68 "name=system,size=768M,uuid=${uuid_gpt_system};" \
69 "name=cache,size=256M,uuid=${uuid_gpt_cache};" \
70 "name=ipu1,size=1M,uuid=${uuid_gpt_ipu1};" \
71 "name=ipu2,size=1M,uuid=${uuid_gpt_ipu2};" \
72 "name=userdata,size=-,uuid=${uuid_gpt_userdata}"
73
74 #define DFUARGS \
75 "dfu_bufsiz=0x10000\0" \
76 DFU_ALT_INFO_MMC \
77 DFU_ALT_INFO_EMMC \
78 DFU_ALT_INFO_RAM \
79 DFU_ALT_INFO_QSPI
80 #else
81 /* Discard fastboot in SPL build, to spare some space */
82 #undef CONFIG_FASTBOOT
83 #undef CONFIG_USB_FUNCTION_FASTBOOT
84 #undef CONFIG_CMD_FASTBOOT
85 #undef CONFIG_ANDROID_BOOT_IMAGE
86 #undef CONFIG_FASTBOOT_BUF_ADDR
87 #undef CONFIG_FASTBOOT_BUF_SIZE
88 #undef CONFIG_FASTBOOT_FLASH
89 #endif
90
91 #ifdef CONFIG_SPL_BUILD
92 #undef CONFIG_CMD_BOOTD
93 #ifdef CONFIG_SPL_DFU_SUPPORT
94 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000
95 #define DFUARGS \
96 "dfu_bufsiz=0x10000\0" \
97 DFU_ALT_INFO_RAM
98 #endif
99 #endif
100
101 #include <configs/ti_omap5_common.h>
102
103 /* Enhance our eMMC support / experience. */
104 #define CONFIG_RANDOM_UUID
105 #define CONFIG_HSMMC2_8BIT
106
107 /* CPSW Ethernet */
108 #define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
109 #define CONFIG_BOOTP_DNS2
110 #define CONFIG_BOOTP_SEND_HOSTNAME
111 #define CONFIG_BOOTP_GATEWAY
112 #define CONFIG_BOOTP_SUBNETMASK
113 #define CONFIG_NET_RETRY_COUNT 10
114 #define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
115 #define CONFIG_MII /* Required in net/eth.c */
116 #define CONFIG_PHY_GIGE /* per-board part of CPSW */
117 #define CONFIG_PHYLIB
118 #define CONFIG_PHY_TI
119
120 /* SPI */
121 #undef CONFIG_OMAP3_SPI
122 #define CONFIG_TI_SPI_MMAP
123 #define CONFIG_SF_DEFAULT_SPEED 76800000
124 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
125 #define CONFIG_QSPI_QUAD_SUPPORT
126
127 /*
128 * Default to using SPI for environment, etc.
129 * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
130 * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
131 * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
132 * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
133 * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
134 * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
135 * 0x9E0000 - 0x2000000 : USERLAND
136 */
137 #define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000
138 #define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
139 #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
140 #if defined(CONFIG_QSPI_BOOT)
141 #define CONFIG_ENV_IS_IN_SPI_FLASH
142 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
143 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
144 #define CONFIG_ENV_SIZE (64 << 10)
145 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */
146 #define CONFIG_ENV_OFFSET 0x1C0000
147 #define CONFIG_ENV_OFFSET_REDUND 0x1D0000
148 #endif
149
150 /* SPI SPL */
151 #define CONFIG_TI_EDMA3
152 #define CONFIG_SPL_SPI_LOAD
153 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
154
155 #define CONFIG_SUPPORT_EMMC_BOOT
156
157 /* USB xHCI HOST */
158 #define CONFIG_USB_XHCI_OMAP
159 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
160
161 #define CONFIG_OMAP_USB_PHY
162 #define CONFIG_OMAP_USB2PHY2_HOST
163
164 /* SATA */
165 #define CONFIG_SCSI
166 #define CONFIG_LIBATA
167 #define CONFIG_SCSI_AHCI
168 #define CONFIG_SCSI_AHCI_PLAT
169 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
170 #define CONFIG_SYS_SCSI_MAX_LUN 1
171 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
172 CONFIG_SYS_SCSI_MAX_LUN)
173
174 /* NAND support */
175 #ifdef CONFIG_NAND
176 /* NAND: device related configs */
177 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
178 #define CONFIG_SYS_NAND_OOBSIZE 64
179 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
180 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
181 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
182 CONFIG_SYS_NAND_PAGE_SIZE)
183 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
184 /* NAND: driver related configs */
185 #define CONFIG_NAND_OMAP_GPMC
186 #define CONFIG_NAND_OMAP_ELM
187 #define CONFIG_SYS_NAND_ONFI_DETECTION
188 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
189 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
190 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
191 10, 11, 12, 13, 14, 15, 16, 17, \
192 18, 19, 20, 21, 22, 23, 24, 25, \
193 26, 27, 28, 29, 30, 31, 32, 33, \
194 34, 35, 36, 37, 38, 39, 40, 41, \
195 42, 43, 44, 45, 46, 47, 48, 49, \
196 50, 51, 52, 53, 54, 55, 56, 57, }
197 #define CONFIG_SYS_NAND_ECCSIZE 512
198 #define CONFIG_SYS_NAND_ECCBYTES 14
199 #define MTDIDS_DEFAULT "nand0=nand.0"
200 #define MTDPARTS_DEFAULT "mtdparts=nand.0:" \
201 "128k(NAND.SPL)," \
202 "128k(NAND.SPL.backup1)," \
203 "128k(NAND.SPL.backup2)," \
204 "128k(NAND.SPL.backup3)," \
205 "256k(NAND.u-boot-spl-os)," \
206 "1m(NAND.u-boot)," \
207 "128k(NAND.u-boot-env)," \
208 "128k(NAND.u-boot-env.backup1)," \
209 "8m(NAND.kernel)," \
210 "-(NAND.file-system)"
211 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
212 /* NAND: SPL related configs */
213 #ifdef CONFIG_SPL_NAND_SUPPORT
214 #define CONFIG_SPL_NAND_AM33XX_BCH
215 #endif
216 /* NAND: SPL falcon mode configs */
217 #ifdef CONFIG_SPL_OS_BOOT
218 #define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os-boot params*/
219 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
220 #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
221 #endif
222 #endif /* !CONFIG_NAND */
223
224 /* Parallel NOR Support */
225 #if defined(CONFIG_NOR)
226 /* NOR: device related configs */
227 #define CONFIG_SYS_MAX_FLASH_SECT 512
228 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
229 #define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */
230 /* #define CONFIG_INIT_IGNORE_ERROR */
231 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
232 #define CONFIG_SYS_FLASH_PROTECTION
233 #define CONFIG_SYS_FLASH_CFI
234 #define CONFIG_FLASH_CFI_DRIVER
235 #define CONFIG_FLASH_CFI_MTD
236 #define CONFIG_SYS_MAX_FLASH_BANKS 1
237 #define CONFIG_SYS_FLASH_BASE (0x08000000)
238 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
239 /* Reduce SPL size by removing unlikey targets */
240 #ifdef CONFIG_NOR_BOOT
241 #define CONFIG_ENV_IS_IN_FLASH
242 #define CONFIG_ENV_SECT_SIZE (128 * 1024) /* 128 KiB */
243 #define MTDIDS_DEFAULT "nor0=physmap-flash.0"
244 #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \
245 "128k(NOR.SPL)," \
246 "128k(NOR.SPL.backup1)," \
247 "128k(NOR.SPL.backup2)," \
248 "128k(NOR.SPL.backup3)," \
249 "256k(NOR.u-boot-spl-os)," \
250 "1m(NOR.u-boot)," \
251 "128k(NOR.u-boot-env)," \
252 "128k(NOR.u-boot-env.backup1)," \
253 "8m(NOR.kernel)," \
254 "-(NOR.rootfs)"
255 #define CONFIG_ENV_OFFSET 0x001c0000
256 #define CONFIG_ENV_OFFSET_REDUND 0x001e0000
257 #endif
258 #endif /* NOR support */
259
260 #endif /* __CONFIG_DRA7XX_EVM_H */