include/configs/eb_cpu5282.h

   1 /*
   2  * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
   3  *
   4  * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef _CONFIG_EB_CPU5282_H_
  10 #define _CONFIG_EB_CPU5282_H_
  11
  12 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
  13
  14 /*----------------------------------------------------------------------*
  15  * High Level Configuration Options (easy to change)                    *
  16  *----------------------------------------------------------------------*/
  17
  18 #define CONFIG_MISC_INIT_R
  19
  20 #define CONFIG_MCFUART
  21 #define CONFIG_SYS_UART_PORT            (0)
  22 #define CONFIG_BAUDRATE                 115200
  23
  24 #undef  CONFIG_MONITOR_IS_IN_RAM                /* starts uboot direct */
  25
  26 #define CONFIG_BOOTCOMMAND "printenv"
  27
  28 /*----------------------------------------------------------------------*
  29  * Options                                                              *
  30  *----------------------------------------------------------------------*/
  31
  32 #define CONFIG_BOOT_RETRY_TIME  -1
  33 #define CONFIG_RESET_TO_RETRY
  34 #define CONFIG_SPLASH_SCREEN
  35
  36 #define CONFIG_HW_WATCHDOG
  37
  38 #define CONFIG_STATUS_LED
  39 #define CONFIG_BOARD_SPECIFIC_LED
  40 #define STATUS_LED_ACTIVE               0
  41 #define STATUS_LED_BIT                  0x0008  /* Timer7 GPIO */
  42 #define STATUS_LED_BOOT                 0
  43 #define STATUS_LED_PERIOD               (CONFIG_SYS_HZ / 2)
  44 #define STATUS_LED_STATE                STATUS_LED_OFF
  45
  46 /*----------------------------------------------------------------------*
  47  * Configuration for environment                                        *
  48  * Environment is in the second sector of the first 256k of flash       *
  49  *----------------------------------------------------------------------*/
  50
  51 #define CONFIG_ENV_ADDR         0xFF040000
  52 #define CONFIG_ENV_SECT_SIZE    0x00020000
  53 #define CONFIG_ENV_IS_IN_FLASH  1
  54
  55 /*
  56  * BOOTP options
  57  */
  58 #define CONFIG_BOOTP_BOOTFILESIZE
  59 #define CONFIG_BOOTP_BOOTPATH
  60 #define CONFIG_BOOTP_GATEWAY
  61 #define CONFIG_BOOTP_HOSTNAME
  62
  63 /*
  64  * Command line configuration.
  65  */
  66 #define CONFIG_CMDLINE_EDITING
  67 #define CONFIG_CMD_DATE
  68 #define CONFIG_CMD_DHCP
  69 #define CONFIG_CMD_I2C
  70 #define CONFIG_CMD_LED
  71 #define CONFIG_CMD_MII
  72
  73 #define CONFIG_MCFTMR
  74
  75 #define CONFIG_BOOTDELAY        5
  76 #define CONFIG_SYS_PROMPT       "\nEB+CPU5282> "
  77 #define CONFIG_SYS_LONGHELP     1
  78
  79 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size      */
  80 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  81 #define CONFIG_SYS_MAXARGS      16      /* max number of command args   */
  82 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  83
  84 #define CONFIG_SYS_LOAD_ADDR            0x20000
  85
  86 #define CONFIG_SYS_MEMTEST_START        0x100000
  87 #define CONFIG_SYS_MEMTEST_END          0x400000
  88 /*#define CONFIG_SYS_DRAM_TEST          1 */
  89 #undef CONFIG_SYS_DRAM_TEST
  90
  91 /*----------------------------------------------------------------------*
  92  * Clock and PLL Configuration                                          *
  93  *----------------------------------------------------------------------*/
  94 #define CONFIG_SYS_CLK                  80000000      /* 8MHz * 8 */
  95
  96 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
  97
  98 #define CONFIG_SYS_MFD          0x02    /* PLL Multiplication Factor Devider */
  99 #define CONFIG_SYS_RFD          0x00    /* PLL Reduce Frecuency Devider */
 100
 101 /*----------------------------------------------------------------------*
 102  * Network                                                              *
 103  *----------------------------------------------------------------------*/
 104
 105 #define CONFIG_MCFFEC
 106 #define CONFIG_MII                      1
 107 #define CONFIG_MII_INIT                 1
 108 #define CONFIG_SYS_DISCOVER_PHY
 109 #define CONFIG_SYS_RX_ETH_BUFFER        8
 110 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 111
 112 #define CONFIG_SYS_FEC0_PINMUX          0
 113 #define CONFIG_SYS_FEC0_MIIBASE         CONFIG_SYS_FEC0_IOBASE
 114 #define MCFFEC_TOUT_LOOP                50000
 115
 116 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 117
 118 /*-------------------------------------------------------------------------
 119  * Low Level Configuration Settings
 120  * (address mappings, register initial values, etc.)
 121  * You should know what you are doing if you make changes here.
 122  *-----------------------------------------------------------------------*/
 123
 124 #define CONFIG_SYS_MBAR                 0x40000000
 125
 126 /*-----------------------------------------------------------------------
 127  * Definitions for initial stack pointer and data area (in DPRAM)
 128  *-----------------------------------------------------------------------*/
 129
 130 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 131 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
 132 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 133         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 134 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 135
 136 /*-----------------------------------------------------------------------
 137  * Start addresses for the final memory configuration
 138  * (Set up by the startup code)
 139  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 140  */
 141 #define CONFIG_SYS_SDRAM_BASE0          0x00000000
 142 #define CONFIG_SYS_SDRAM_SIZE0          16      /* SDRAM size in MB */
 143
 144 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_SDRAM_BASE0
 145 #define CONFIG_SYS_SDRAM_SIZE           CONFIG_SYS_SDRAM_SIZE0
 146
 147 #define CONFIG_SYS_MONITOR_LEN          0x20000
 148 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 149 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 150
 151 /*
 152  * For booting Linux, the board info and command line data
 153  * have to be in the first 8 MB of memory, since this is
 154  * the maximum mapped by the Linux kernel during initialization ??
 155  */
 156 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20) /* Initial Memory map for Linux */
 157
 158 /*-----------------------------------------------------------------------
 159  * FLASH organization
 160  */
 161 #define CONFIG_FLASH_SHOW_PROGRESS      45
 162
 163 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 164 #define CONFIG_SYS_INT_FLASH_BASE       0xF0000000
 165 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
 166
 167 #define CONFIG_SYS_MAX_FLASH_SECT       128
 168 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 169 #define CONFIG_SYS_FLASH_ERASE_TOUT     10000000
 170 #define CONFIG_SYS_FLASH_PROTECTION
 171
 172 #define CONFIG_SYS_FLASH_CFI
 173 #define CONFIG_FLASH_CFI_DRIVER
 174 #define CONFIG_SYS_FLASH_SIZE           16*1024*1024
 175 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 176
 177 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 178
 179 /*-----------------------------------------------------------------------
 180  * Cache Configuration
 181  */
 182 #define CONFIG_SYS_CACHELINE_SIZE       16
 183
 184 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 185                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 186 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 187                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 188 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 189 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 190                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 191                                          CF_ACR_EN | CF_ACR_SM_ALL)
 192 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 193                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 194                                          CF_CACR_EUSP)
 195
 196 /*-----------------------------------------------------------------------
 197  * Memory bank definitions
 198  */
 199
 200 #define CONFIG_SYS_CS0_BASE             0xFF000000
 201 #define CONFIG_SYS_CS0_CTRL             0x00001980
 202 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 203
 204 #define CONFIG_SYS_CS2_BASE             0xE0000000
 205 #define CONFIG_SYS_CS2_CTRL             0x00001980
 206 #define CONFIG_SYS_CS2_MASK             0x000F0001
 207
 208 #define CONFIG_SYS_CS3_BASE             0xE0100000
 209 #define CONFIG_SYS_CS3_CTRL             0x00001980
 210 #define CONFIG_SYS_CS3_MASK             0x000F0001
 211
 212 /*-----------------------------------------------------------------------
 213  * Port configuration
 214  */
 215 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 216 #define CONFIG_SYS_PADDR                0x0000000
 217 #define CONFIG_SYS_PADAT                0x0000000
 218
 219 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 220 #define CONFIG_SYS_PBDDR                0x0000000
 221 #define CONFIG_SYS_PBDAT                0x0000000
 222
 223 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 224 #define CONFIG_SYS_PCDDR                0x0000000
 225 #define CONFIG_SYS_PCDAT                0x0000000
 226
 227 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 228 #define CONFIG_SYS_PCDDR                0x0000000
 229 #define CONFIG_SYS_PCDAT                0x0000000
 230
 231 #define CONFIG_SYS_PASPAR               0x0F0F
 232 #define CONFIG_SYS_PEHLPAR              0xC0
 233 #define CONFIG_SYS_PUAPAR               0x0F
 234 #define CONFIG_SYS_DDRUA                0x05
 235 #define CONFIG_SYS_PJPAR                0xFF
 236
 237 /*-----------------------------------------------------------------------
 238  * I2C
 239  */
 240
 241 #define CONFIG_SYS_I2C
 242 #define CONFIG_SYS_I2C_FSL
 243
 244 #define CONFIG_SYS_FSL_I2C_OFFSET       0x00000300
 245 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 246
 247 #define CONFIG_SYS_FSL_I2C_SPEED        100000
 248 #define CONFIG_SYS_FSL_I2C_SLAVE        0
 249
 250 #ifdef CONFIG_CMD_DATE
 251 #define CONFIG_RTC_DS1338
 252 #define CONFIG_I2C_RTC_ADDR             0x68
 253 #endif
 254
 255 /*-----------------------------------------------------------------------
 256  * VIDEO configuration
 257  */
 258
 259 #define CONFIG_VIDEO
 260
 261 #ifdef CONFIG_VIDEO
 262 #define CONFIG_VIDEO_VCXK                       1
 263
 264 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       2
 265 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED          1
 266 #define CONFIG_SYS_VCXK_BASE                    CONFIG_SYS_CS2_BASE
 267
 268 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        MCFGPTB_GPTPORT
 269 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         MCFGPTB_GPTDDR
 270 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         0x0001
 271
 272 #define CONFIG_SYS_VCXK_ENABLE_PORT             MCFGPTB_GPTPORT
 273 #define CONFIG_SYS_VCXK_ENABLE_DDR              MCFGPTB_GPTDDR
 274 #define CONFIG_SYS_VCXK_ENABLE_PIN              0x0002
 275
 276 #define CONFIG_SYS_VCXK_REQUEST_PORT            MCFGPTB_GPTPORT
 277 #define CONFIG_SYS_VCXK_REQUEST_DDR             MCFGPTB_GPTDDR
 278 #define CONFIG_SYS_VCXK_REQUEST_PIN             0x0004
 279
 280 #define CONFIG_SYS_VCXK_INVERT_PORT             MCFGPIO_PORTE
 281 #define CONFIG_SYS_VCXK_INVERT_DDR              MCFGPIO_DDRE
 282 #define CONFIG_SYS_VCXK_INVERT_PIN              MCFGPIO_PORT2
 283
 284 #endif /* CONFIG_VIDEO */
 285 #endif  /* _CONFIG_M5282EVB_H */
 286 /*---------------------------------------------------------------------*/