include/configs/eb_cpux9k2.h

   1 /*
   2  * (C) Copyright 2008-2009
   3  * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
   4  * Jens Scharsig <esw@bus-elektronik.de>
   5  *
   6  * Configuation settings for the EB+CPUx9K2 board.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef _CONFIG_EB_CPUx9K2_H_
  12 #define _CONFIG_EB_CPUx9K2_H_
  13
  14 /*--------------------------------------------------------------------------*/
  15
  16 #define CONFIG_AT91RM9200               /* It's an Atmel AT91RM9200 SoC */
  17 #define CONFIG_EB_CPUX9K2               /* on an EP+CPUX9K2 Board       */
  18 #define USE_920T_MMU
  19
  20 #define CONFIG_VERSION_VARIABLE
  21 #define CONFIG_IDENT_STRING     " on EB+CPUx9K2"
  22
  23 #include <asm/hardware.h>       /* needed for port definitions */
  24
  25 #define CONFIG_MISC_INIT_R
  26 #define CONFIG_BOARD_EARLY_INIT_F
  27
  28 #define MACH_TYPE_EB_CPUX9K2            1977
  29 #define CONFIG_MACH_TYPE                MACH_TYPE_EB_CPUX9K2
  30
  31 #define CONFIG_SYS_CACHELINE_SIZE       32
  32 #define CONFIG_SYS_DCACHE_OFF
  33
  34 /*--------------------------------------------------------------------------*/
  35 #ifndef CONFIG_RAMBOOT
  36 #define CONFIG_SYS_TEXT_BASE            0x00000000
  37 #else
  38 #define CONFIG_SKIP_LOWLEVEL_INIT
  39 #define CONFIG_SYS_TEXT_BASE            0x21f00000
  40 #endif
  41 #define CONFIG_SYS_LOAD_ADDR            0x21000000  /* default load address */
  42
  43 #define CONFIG_SYS_BOOT_SIZE            0x00 /* 0 KBytes */
  44 #define CONFIG_SYS_U_BOOT_BASE          PHYS_FLASH_1
  45 #define CONFIG_SYS_U_BOOT_SIZE          0x60000 /* 384 KBytes */
  46
  47 #define CONFIG_BOOT_RETRY_TIME          30
  48 #define CONFIG_CMDLINE_EDITING
  49
  50 #define CONFIG_SYS_PROMPT       "U-Boot> "      /* Monitor Command Prompt */
  51 #define CONFIG_SYS_CBSIZE       512             /* Console I/O Buffer Size */
  52 #define CONFIG_SYS_MAXARGS      32              /* max number of command args */
  53 #define CONFIG_SYS_PBSIZE       \
  54         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  55
  56 /*
  57  * ARM asynchronous clock
  58  */
  59
  60 #define AT91C_MAIN_CLOCK        179404800       /* from 12.288 MHz * 73 / 5 */
  61 #define AT91C_MASTER_CLOCK      (AT91C_MAIN_CLOCK / 3)
  62 #define CONFIG_SYS_HZ           1000
  63 #define CONFIG_SYS_HZ_CLOCK     (AT91C_MASTER_CLOCK / 2)
  64
  65 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock */
  66
  67 #define CONFIG_CMDLINE_TAG              1
  68 #define CONFIG_SETUP_MEMORY_TAGS        1
  69 #define CONFIG_INITRD_TAG               1
  70
  71 #define CONFIG_SYS_USE_MAIN_OSCILLATOR  1
  72 /* flash */
  73 #define CONFIG_SYS_EBI_CFGR_VAL         0x00000000
  74 #define CONFIG_SYS_SMC_CSR0_VAL         0x00003284 /* 16bit, 2 TDF, 4 WS */
  75
  76 /* clocks */
  77 #define CONFIG_SYS_PLLAR_VAL            0x20483E05 /* 179.4048 MHz for PCK */
  78 #define CONFIG_SYS_PLLBR_VAL            0x104C3E0A /* 47.3088 MHz (for USB) */
  79 #define CONFIG_SYS_MCKR_VAL             0x00000202 /* PCK/3 = MCK Clock */
  80
  81 /*
  82  * Size of malloc() pool
  83  */
  84
  85 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 520*1024)
  86
  87 /*
  88  * sdram
  89  */
  90
  91 #define CONFIG_NR_DRAM_BANKS            1
  92
  93 #define CONFIG_SYS_SDRAM_BASE           0x20000000
  94 #define CONFIG_SYS_SDRAM_SIZE           0x04000000  /* 64 megs */
  95 #define CONFIG_SYS_INIT_SP_ADDR         0x00204000  /* use internal SRAM */
  96
  97 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
  98 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
  99                                         CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
 100                                         CONFIG_SYS_MALLOC_LEN)
 101
 102 #define CONFIG_SYS_PIOC_ASR_VAL         0xFFFF0000 /* PIOC as D16/D31 */
 103 #define CONFIG_SYS_PIOC_BSR_VAL         0x00000000
 104 #define CONFIG_SYS_PIOC_PDR_VAL         0xFFFF0000
 105 #define CONFIG_SYS_EBI_CSA_VAL          0x00000002 /* CS1=SDRAM */
 106 #define CONFIG_SYS_SDRC_CR_VAL          0x2188c159 /* set up the SDRAM */
 107 #define CONFIG_SYS_SDRAM                0x20000000 /* address of the SDRAM */
 108 #define CONFIG_SYS_SDRAM1               0x20000080 /* address of the SDRAM */
 109 #define CONFIG_SYS_SDRAM_VAL            0x00000000 /* value written to SDRAM */
 110 #define CONFIG_SYS_SDRC_MR_VAL          0x00000002 /* Precharge All */
 111 #define CONFIG_SYS_SDRC_MR_VAL1         0x00000004 /* refresh */
 112 #define CONFIG_SYS_SDRC_MR_VAL2         0x00000003 /* Load Mode Register */
 113 #define CONFIG_SYS_SDRC_MR_VAL3         0x00000000 /* Normal Mode */
 114 #define CONFIG_SYS_SDRC_TR_VAL          0x000002E0 /* Write refresh rate */
 115
 116 /*
 117  * Command line configuration
 118  */
 119
 120 #include <config_cmd_default.h>
 121
 122 #define CONFIG_CMD_BMP
 123 #define CONFIG_CMD_DATE
 124 #define CONFIG_CMD_DHCP
 125 #define CONFIG_CMD_I2C
 126 #define CONFIG_CMD_JFFS2
 127 #define CONFIG_CMD_MII
 128 #define CONFIG_CMD_NAND
 129 #define CONFIG_CMD_PING
 130 #define CONFIG_I2C_CMD_NO_FLAT
 131 #define CONFIG_I2C_CMD_TREE
 132 #define CONFIG_CMD_USB
 133 #define CONFIG_CMD_FAT
 134
 135 #define CONFIG_SYS_LONGHELP
 136
 137 /*
 138  * Filesystems
 139  */
 140
 141 #define CONFIG_JFFS2_NAND               1
 142
 143 #ifndef CONFIG_JFFS2_CMDLINE
 144 #define CONFIG_JFFS2_DEV                "nand0"
 145 #define CONFIG_JFFS2_PART_OFFSET        0
 146 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 147 #else
 148 #define MTDIDS_DEFAULT          "nor0=0,nand0=1"
 149 #define MTDPARTS_DEFAULT        "mtdparts="                             \
 150                                         "0:"                            \
 151                                         "384k(U-Boot),"                 \
 152                                         "128k(Env),"                    \
 153                                         "128k(Splash),"                 \
 154                                         "4M(Kernel),"                   \
 155                                         "-(FS)"                         \
 156                                         ";"                             \
 157                                         "1:"                            \
 158                                         "-(jffs2)"
 159 #endif /* CONFIG_JFFS2_CMDLINE */
 160
 161 /*
 162  * Hardware drivers
 163  */
 164 #define CONFIG_USB_ATMEL
 165 #define CONFIG_USB_OHCI_NEW
 166 #define CONFIG_AT91C_PQFP_UHPBUG
 167 #define CONFIG_USB_STORAGE
 168 #define CONFIG_DOS_PARTITION
 169 #define CONFIG_ISO_PARTITION
 170 #define CONFIG_EFI_PARTITION
 171
 172 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      1
 173 #define CONFIG_SYS_USB_OHCI_CPU_INIT
 174 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00300000
 175 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91rm9200"
 176
 177 /*
 178  * UART/CONSOLE
 179  */
 180
 181 #define CONFIG_BAUDRATE 115200
 182 #define CONFIG_ATMEL_USART
 183 #define CONFIG_USART_BASE       ATMEL_BASE_DBGU
 184 #define CONFIG_USART_ID         0/* ignored in arm */
 185
 186 /*
 187  * network
 188  */
 189
 190 #define CONFIG_NET_RETRY_COUNT          10
 191 #define CONFIG_RESET_PHY_R              1
 192
 193 #define CONFIG_DRIVER_AT91EMAC          1
 194 #define CONFIG_DRIVER_AT91EMAC_QUIET    1
 195 #define CONFIG_SYS_RX_ETH_BUFFER        8
 196 #define CONFIG_MII                      1
 197
 198 /*
 199  * BOOTP options
 200  */
 201 #define CONFIG_BOOTP_BOOTFILESIZE
 202 #define CONFIG_BOOTP_BOOTPATH
 203 #define CONFIG_BOOTP_GATEWAY
 204 #define CONFIG_BOOTP_HOSTNAME
 205
 206 /*
 207  * I2C-Bus
 208  */
 209
 210 #define CONFIG_SYS_I2C_SPEED            50000
 211 #define CONFIG_SYS_I2C_SLAVE            0               /* not used */
 212
 213 #ifndef CONFIG_HARD_I2C
 214 #define CONFIG_SOFT_I2C
 215
 216 /* Software  I2C driver configuration */
 217
 218 #define AT91_PIN_SDA                    (1<<25)         /* AT91C_PIO_PA25 */
 219 #define AT91_PIN_SCL                    (1<<26)         /* AT91C_PIO_PA26 */
 220
 221 #define CONFIG_SYS_I2C_INIT_BOARD
 222
 223 #define I2C_INIT        i2c_init_board();
 224 #define I2C_ACTIVE      writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr);
 225 #define I2C_TRISTATE    writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder);
 226 #define I2C_READ        ((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0)
 227 #define I2C_SDA(bit)                                            \
 228         if (bit)                                                \
 229                 writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr);      \
 230         else                                                    \
 231                 writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr);
 232 #define I2C_SCL(bit)                                            \
 233         if (bit)                                                \
 234                 writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr);     \
 235         else                                                    \
 236                 writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr);
 237
 238 #define I2C_DELAY       udelay(2500000/CONFIG_SYS_I2C_SPEED)
 239
 240 #endif  /* CONFIG_HARD_I2C */
 241
 242 /* I2C-RTC */
 243
 244 #ifdef CONFIG_CMD_DATE
 245 #define CONFIG_RTC_DS1338
 246 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 247 #endif
 248
 249 /* EEPROM */
 250
 251 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 252 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 253
 254 /* FLASH organization */
 255
 256 /*  NOR-FLASH */
 257 #define CONFIG_FLASH_SHOW_PROGRESS      45
 258
 259 #define CONFIG_FLASH_CFI_DRIVER 1
 260
 261 #define PHYS_FLASH_1                    0x10000000
 262 #define PHYS_FLASH_SIZE                 0x01000000  /* 16 megs main flash */
 263 #define CONFIG_SYS_FLASH_CFI            1
 264 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 265
 266 #define CONFIG_SYS_FLASH_PROTECTION     1
 267 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 268 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 269 #define CONFIG_SYS_MAX_FLASH_SECT       512
 270 #define CONFIG_SYS_FLASH_ERASE_TOUT     6000
 271 #define CONFIG_SYS_FLASH_WRITE_TOUT     2000
 272
 273 /* NAND */
 274
 275 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 276 #define CONFIG_SYS_NAND_BASE            0x40000000
 277 #define CONFIG_SYS_NAND_DBW_8           1
 278
 279 /* Status LED's */
 280
 281 #define CONFIG_STATUS_LED               1
 282 #define CONFIG_BOARD_SPECIFIC_LED       1
 283
 284 #define STATUS_LED_BOOT                 1
 285 #define STATUS_LED_ACTIVE               0
 286
 287 #define STATUS_LED_BIT                  1       /* AT91C_PIO_PD0 green LED */
 288 #define STATUS_LED_PERIOD               (CONFIG_SYS_HZ / 2)
 289 #define STATUS_LED_STATE                STATUS_LED_OFF          /* BLINKING */
 290 #define STATUS_LED_BIT1                 2       /* AT91C_PIO_PD1  red LED */
 291 #define STATUS_LED_STATE1               STATUS_LED_ON           /* BLINKING */
 292 #define STATUS_LED_PERIOD1              (CONFIG_SYS_HZ / 4)
 293
 294 #define CONFIG_VIDEO                    1
 295
 296 /* Options */
 297
 298 #ifdef CONFIG_VIDEO
 299
 300 #define CONFIG_VIDEO_VCXK                       1
 301
 302 #define CONFIG_SPLASH_SCREEN                    1
 303
 304 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       4
 305 #define CONFIG_SYS_VCXK_BASE    0x30000000
 306
 307 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         (1<<3)
 308 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        piob
 309 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         odr
 310
 311 #define CONFIG_SYS_VCXK_ENABLE_PIN              (1<<5)
 312 #define CONFIG_SYS_VCXK_ENABLE_PORT             piob
 313 #define CONFIG_SYS_VCXK_ENABLE_DDR              oer
 314
 315 #define CONFIG_SYS_VCXK_REQUEST_PIN             (1<<2)
 316 #define CONFIG_SYS_VCXK_REQUEST_PORT            piob
 317 #define CONFIG_SYS_VCXK_REQUEST_DDR             oer
 318
 319 #define CONFIG_SYS_VCXK_INVERT_PIN              (1<<4)
 320 #define CONFIG_SYS_VCXK_INVERT_PORT             piob
 321 #define CONFIG_SYS_VCXK_INVERT_DDR              oer
 322
 323 #define CONFIG_SYS_VCXK_RESET_PIN               (1<<6)
 324 #define CONFIG_SYS_VCXK_RESET_PORT              piob
 325 #define CONFIG_SYS_VCXK_RESET_DDR               oer
 326
 327 #endif  /* CONFIG_VIDEO */
 328
 329 /* Environment */
 330
 331 #define CONFIG_BOOTDELAY                5
 332
 333 #define CONFIG_ENV_IS_IN_FLASH          1
 334 #define CONFIG_ENV_ADDR                 (PHYS_FLASH_1 + 0x60000)
 335 #define CONFIG_ENV_SIZE                 0x20000 /* sectors are 128K here */
 336
 337 #define CONFIG_BAUDRATE                 115200
 338
 339 #define CONFIG_BOOTCOMMAND              "run nfsboot"
 340
 341 #define CONFIG_NFSBOOTCOMMAND                                           \
 342                 "dhcp $(copy_addr) uImage_cpux9k2;"                     \
 343                 "run bootargsdefaults;"                                 \
 344                 "set bootargs $(bootargs) boot=nfs "                    \
 345                 ";echo $(bootargs)"                                     \
 346         ";bootm"
 347
 348 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 349         "displaywidth=256\0"                                            \
 350         "displayheight=512\0"                                           \
 351         "displaybsteps=1023\0"                                          \
 352         "ubootaddr=10000000\0"                                          \
 353         "splashimage=10080000\0"                                        \
 354         "kerneladdr=100A0000\0"                                         \
 355         "kernelsize=00400000\0"                                         \
 356         "rootfsaddr=104A0000\0"                                         \
 357         "copy_addr=21200000\0"                                          \
 358         "rootfssize=00B60000\0"                                         \
 359         "bootargsdefaults=set bootargs "                                \
 360                 "console=ttyS0,115200 "                                 \
 361                 "video=vcxk_fb:xres:${displaywidth},"                   \
 362                         "yres:${displayheight},"                        \
 363                         "bres:${displaybsteps} "                        \
 364                 "mem=62M "                                              \
 365                 "panic=10 "                                             \
 366                 "uboot=\\\"${ver}\\\" "                                 \
 367                 "\0"                                                    \
 368         "update_kernel=protect off $(kerneladdr) +$(kernelsize);"       \
 369                 "dhcp $(copy_addr) uImage_cpux9k2;"                     \
 370                 "erase $(kerneladdr) +$(kernelsize);"                   \
 371                 "cp.b $(fileaddr) $(kerneladdr) $(filesize);"           \
 372                 "protect on $(kerneladdr) +$(kernelsize)"               \
 373                 "\0"                                                    \
 374         "update_root=protect off $(rootfsaddr) +$(rootfssize);"         \
 375                 "dhcp $(copy_addr) rfs;"                                \
 376                 "erase $(rootfsaddr) +$(rootfssize);"                   \
 377                 "cp.b $(fileaddr) $(rootfsaddr) $(filesize);"           \
 378                 "\0"                                                    \
 379         "update_uboot=protect off 10000000 1005FFFF;"                   \
 380                 "dhcp $(copy_addr) u-boot_eb_cpux9k2;"                  \
 381                 "erase 10000000 1005FFFF;"                              \
 382                 "cp.b $(fileaddr) $(ubootaddr) $(filesize);"            \
 383                 "protect on 10000000 1005FFFF;reset\0"                  \
 384         "update_splash=protect off $(splashimage) +20000;"              \
 385                 "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;"              \
 386                 "erase $(splashimage) +20000;"                          \
 387                 "cp.b $(fileaddr) 10080000 $(filesize);"                \
 388                 "protect on $(splashimage) +20000;reset\0"              \
 389         "emergency=run bootargsdefaults;"                               \
 390                 "set bootargs $(bootargs) root=initramfs boot=emergency " \
 391                 ";bootm $(kerneladdr)\0"                                \
 392         "netemergency=run bootargsdefaults;"                            \
 393                 "dhcp $(copy_addr) uImage_cpux9k2;"                     \
 394                 "set bootargs $(bootargs) root=initramfs boot=emergency " \
 395                 ";bootm $(copy_addr)\0"                                 \
 396         "norboot=run bootargsdefaults;"                                 \
 397                 "set bootargs $(bootargs) root=initramfs boot=local "   \
 398                 ";bootm $(kerneladdr)\0"                                \
 399         "nandboot=run bootargsdefaults;"                                \
 400                 "set bootargs $(bootargs) root=initramfs boot=nand "    \
 401                 ";bootm $(kerneladdr)\0"                                \
 402         " "
 403
 404 /*--------------------------------------------------------------------------*/
 405
 406 #endif
 407
 408 /* EOF */