include/configs/ep8248.h

   1 /*
   2  * Copyright (C) 2004 Arabella Software Ltd.
   3  * Yuli Barcohen <yuli@arabellasw.com>
   4  *
   5  * U-Boot configuration for Embedded Planet EP8248 boards.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 #define CONFIG_MPC8248
  30 #define CPU_ID_STR              "MPC8248"
  31
  32 #define CONFIG_EP8248                   /* Embedded Planet EP8248 board */
  33
  34 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  35
  36 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  37
  38 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
  39 #define CONFIG_ENV_OVERWRITE
  40
  41 /*
  42  * Select serial console configuration
  43  *
  44  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  45  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  46  * for SCC).
  47  */
  48 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
  49 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
  50 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
  51 #define CONFIG_CONS_INDEX       1       /* SMC1 is used for console  */
  52
  53 #define CONFIG_SYS_BCSR         0xFA000000
  54
  55 /* Pass open firmware flat device tree */
  56 #define CONFIG_OF_LIBFDT        1
  57 #define CONFIG_OF_BOARD_SETUP   1
  58
  59 #define OF_TBCLK        (bd->bi_busfreq / 4)
  60 #define OF_STDOUT_PATH  "/soc/cpm/serial <at> 11a80"
  61
  62 /* Select ethernet configuration */
  63 #undef  CONFIG_ETHER_ON_SCC             /* Ethernet is not on SCC */
  64 #define CONFIG_ETHER_ON_FCC             /* Ethernet is on FCC     */
  65 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
  66
  67 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
  68 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
  69
  70 #define CONFIG_HAS_ETH0
  71 #define CONFIG_ETHER_ON_FCC1            1
  72 /* - Rx clock is CLK10
  73  * - Tx clock is CLK11
  74  * - BDs/buffers on 60x bus
  75  * - Full duplex
  76  */
  77 #define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
  78 #define CONFIG_SYS_CMXFCR_VALUE1        (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
  79
  80 #define CONFIG_HAS_ETH1
  81 #define CONFIG_ETHER_ON_FCC2            1
  82 /* - Rx clock is CLK13
  83  * - Tx clock is CLK14
  84  * - BDs/buffers on 60x bus
  85  * - Full duplex
  86  */
  87 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  88 #define CONFIG_SYS_CMXFCR_VALUE2        (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  89
  90 #define CONFIG_MII                      /* MII PHY management        */
  91 #define CONFIG_BITBANGMII               /* Bit-banged MDIO interface */
  92 /*
  93  * GPIO pins used for bit-banged MII communications
  94  */
  95 #define MDIO_PORT               0       /* Not used - implemented in BCSR */
  96
  97 #define MDIO_ACTIVE             (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
  98 #define MDIO_TRISTATE           (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
  99 #define MDIO_READ               (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
 100
 101 #define MDIO(bit)               if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
 102                                 else    *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
 103
 104 #define MDC(bit)                if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
 105                                 else    *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
 106
 107 #define MIIDELAY                udelay(1)
 108
 109 #ifndef CONFIG_8260_CLKIN
 110 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
 111 #endif
 112
 113 #define CONFIG_BAUDRATE         38400
 114
 115
 116 /*
 117  * BOOTP options
 118  */
 119 #define CONFIG_BOOTP_BOOTFILESIZE
 120 #define CONFIG_BOOTP_BOOTPATH
 121 #define CONFIG_BOOTP_GATEWAY
 122 #define CONFIG_BOOTP_HOSTNAME
 123
 124
 125 /*
 126  * Command line configuration.
 127  */
 128 #include <config_cmd_default.h>
 129
 130 #define CONFIG_CMD_DHCP
 131 #define CONFIG_CMD_ECHO
 132 #define CONFIG_CMD_I2C
 133 #define CONFIG_CMD_IMMAP
 134 #define CONFIG_CMD_MII
 135 #define CONFIG_CMD_PING
 136
 137
 138 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 139 #define CONFIG_BOOTCOMMAND      "bootm FF860000"        /* autoboot command */
 140 #define CONFIG_BOOTARGS         "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
 141
 142 #if defined(CONFIG_CMD_KGDB)
 143 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 144 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 145 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 146 #define CONFIG_KGDB_INDEX       1       /* which serial channel for kgdb */
 147 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 148 #endif
 149
 150 #define CONFIG_BZIP2    /* include support for bzip2 compressed images */
 151 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 152
 153 /*
 154  * Miscellaneous configurable options
 155  */
 156 #define CONFIG_SYS_HUSH_PARSER
 157 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 158 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 159 #if defined(CONFIG_CMD_KGDB)
 160 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 161 #else
 162 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 163 #endif
 164 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size  */
 165 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 166 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size  */
 167
 168 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 169 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 170
 171 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 172
 173 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 174
 175 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 176
 177 #define CONFIG_SYS_FLASH_BASE           0xFF800000
 178 #define CONFIG_SYS_FLASH_CFI
 179 #define CONFIG_FLASH_CFI_DRIVER
 180 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks       */
 181 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max num of sects on one chip */
 182
 183 #define CONFIG_SYS_DIRECT_FLASH_TFTP
 184
 185 #if defined(CONFIG_CMD_JFFS2)
 186 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
 187 #define CONFIG_SYS_JFFS2_NUM_BANKS      CONFIG_SYS_MAX_FLASH_BANKS
 188 #define CONFIG_SYS_JFFS2_FIRST_SECTOR  0
 189 #define CONFIG_SYS_JFFS2_LAST_SECTOR   62
 190 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
 191 #define CONFIG_SYS_JFFS_CUSTOM_PART
 192 #endif
 193
 194 #if defined(CONFIG_CMD_I2C)
 195 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
 196 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed                    */
 197 #define CONFIG_SYS_I2C_SLAVE            0x7F    /* I2C slave address            */
 198 #endif
 199
 200 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 201 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 202 #define CONFIG_SYS_RAMBOOT
 203 #endif
 204
 205 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256KB for Monitor */
 206
 207 #define CONFIG_ENV_IS_IN_FLASH
 208
 209 #ifdef CONFIG_ENV_IS_IN_FLASH
 210 #define CONFIG_ENV_SECT_SIZE    0x20000
 211 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 212 #endif /* CONFIG_ENV_IS_IN_FLASH */
 213
 214 #define CONFIG_SYS_DEFAULT_IMMR 0x00010000
 215
 216 #define CONFIG_SYS_IMMR         0xF0000000
 217
 218 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 219 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in DPRAM   */
 220 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 221 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 222
 223 /* Hard reset configuration word */
 224 #define CONFIG_SYS_HRCW_MASTER          0x0C40025A /* Not used - provided by FPGA */
 225 /* No slaves */
 226 #define CONFIG_SYS_HRCW_SLAVE1          0
 227 #define CONFIG_SYS_HRCW_SLAVE2          0
 228 #define CONFIG_SYS_HRCW_SLAVE3          0
 229 #define CONFIG_SYS_HRCW_SLAVE4          0
 230 #define CONFIG_SYS_HRCW_SLAVE5          0
 231 #define CONFIG_SYS_HRCW_SLAVE6          0
 232 #define CONFIG_SYS_HRCW_SLAVE7          0
 233
 234 #define CONFIG_SYS_MALLOC_LEN           (4096 << 10)    /* Reserve 4 MB for malloc()    */
 235 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 236
 237 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPUs */
 238 #if defined(CONFIG_CMD_KGDB)
 239 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 240 #endif
 241
 242 #define CONFIG_SYS_HID0_INIT            0
 243 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE)
 244
 245 #define CONFIG_SYS_HID2         0
 246
 247 #define CONFIG_SYS_SIUMCR               0x01240200
 248 #define CONFIG_SYS_SYPCR                0xFFFF0683
 249 #define CONFIG_SYS_BCR                  0x00000000
 250 #define CONFIG_SYS_SCCR         SCCR_DFBRG01
 251
 252 #define CONFIG_SYS_RMR                  RMR_CSRE
 253 #define CONFIG_SYS_TMCNTSC              (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 254 #define CONFIG_SYS_PISCR                (PISCR_PS|PISCR_PTF|PISCR_PTE)
 255 #define CONFIG_SYS_RCCR         0
 256
 257 #define CONFIG_SYS_MPTPR                0x1300
 258 #define CONFIG_SYS_PSDMR                0x82672522
 259 #define CONFIG_SYS_PSRT         0x4B
 260
 261 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 262 #define CONFIG_SYS_SDRAM_BR             (CONFIG_SYS_SDRAM_BASE | 0x00001841)
 263 #define CONFIG_SYS_SDRAM_OR             0xFF0030C0
 264
 265 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | 0x00001801)
 266 #define CONFIG_SYS_OR0_PRELIM           0xFF8008C2
 267 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_BCSR | 0x00000801)
 268 #define CONFIG_SYS_OR2_PRELIM           0xFFF00864
 269
 270 #define CONFIG_SYS_RESET_ADDRESS        0xC0000000
 271
 272 #endif /* __CONFIG_H */